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APL158118GC-TRG Datasheet(PDF) 10 Page - Anpec Electronics Coropration |
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APL158118GC-TRG Datasheet(HTML) 10 Page - Anpec Electronics Coropration |
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10 / 17 page  Copyright © ANPEC Electronics Corp. Rev. B.5 - Mar., 2008 APL1581 www.anpec.com.tw 10 Application Information (Cont.) A low-ESR solid tantalum and aluminum electrolytic capacitor (ESR<1 Ω) works extremely well and provides good transient response and stability over temperature. Ultra-low-ESR capacitors, such as ceramic chip capacitors, may promote unstable or under-damped transient response, but proper ceramic chip capaci- tors placed near loads can be used as decoupling capacitors. The output capacitors are also used to reduce the slew rate of load current and help the APL1581 to minimize variations of the output voltage, improving transient response. For this purpose, the low-ESR capacitors are recommended. Input Capacitors The input capacitors of VCNTL and VIN pins are not required for stability but for supplying surge currents during large load transients, and this will prevent the input rail from drooping and improve the performance of the APL1581. Because parasitic inductors from volt- age sources or other bulk capacitors to the VCNTL and VIN pins will limit the slew rate of the surge cur- rents during large load transients, resulting in voltage drop at VIN and VCNTL pins. A capacitor of 1 µF (ceramic chip capacitor) or greater (aluminum electrolytic capacitor) is recommended and connected near VCNTL pin. For VIN pin, an aluminum electrolytic capacitor (>33 µF) is recommended. It is not necessary to use low-ESR capacitors. More ca- pacitance reduces the variations of the input voltage at VIN pin. Stability and Output Capacitors (Cont.) 1 2 3 4 8 7 6 5 Top layer VOUT plane for Heat Dissipation (La rge r a rea i s better) COUT CIN Solde ring a rea (140mil x 110mil) for bottom pad Vias Vias CCNTL Load Figure 3 Recommended SOP-8P Layout Layout and Thermal Consideration The APL1581 series have internal power and thermal limiting (T J=150 oC typical) circuitry designed to pro- tect the device under overload conditions. However, maximum junction temperature ratings should not be exceeded under continuous normal load conditions. Careful consideration must be given to all sources of thermal resistance from junction to ambient, includ- ing junction-to-case, case-to-heat sink interface, and heat sink resistance itself. See Figure 3 The SOP-8P is a cost-effective package featuring a small size as a standard SOP-8 and a bottom thermal pad to minimize the thermal resistance of the package, being applicable to high current applications. The thermal pad is soldered to the top VOUT plane which may be connected to internal or bottom VOUT plane by vias to reduce the heat sink thermal resistance. Therefore, the printed circuit board (PCB) forms a heat sink and dissipates heat into am- bient air. |
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