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TDA1180 Datasheet(PDF) 9 Page - STMicroelectronics |
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TDA1180 Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 12 page Pin 10 - Vertical sync output The vertical sync pulse, obtained by internal inte- gration of the synchronizing signal, is available at this pin. The output impedance is typically 10k Ω and the lowest amplitude without load is 11V. Pin 11 - Coincidence detector From the oscillator waveform a gate pulse 7 µs wide is taken whose phase position is centered on the horizontal synchronism. The gate pulse not only controls a logic block which permits the sync to reach the oscillator-sync phase comparator only for as long as its duration, but also allows the latching and de-latching conditions of the oscillator to be established.This function is obtained by a coincidence detector which com- pares the phase of the gate pulses with that of the sync. When the two signals are not accurately aligned in time it means that the oscillator is not synchronized. In this case the detector acts on the logic block to eliminate its filtering effect and on the time constant switching block to establish a high impedance on Pin 12 (small time constant of low-pass filter). This latter block also acts on the oscillator-sync phase detector to increase its sensitivity and with it the loop gain of the synchronizing system. In this conditions the phase lock has low noise immunity (wide equivalent noise bandwidth) and rapid pull-in time which allows fairly short synchro- nization times. Once locking has taken place the coincidence de- tector enables the logic block, causes a low imped- ance on Pin 12 and reduces the sensitivity of the phase comparator. In these conditions the phase lock has high noise immunity ( narrow equivalent noise bandwidth) due to the complete elimination of interference which occurs during the scanning period and the greater inertia with which the oscillator can change its frequency. To optimize the behaviour of the IC if a video recorder is used, the state of the detector can be forced by connecting Pin 11 to earth or to + VS. The characteristics of the phase lock thus correspond to the lack of synchronization. Pin 12 - Time constant switch, (see Pin 11) Pin 13 - Control current output The oscillator is synchronized by comparing the phase of its waveform with that of the sync pulses in the oscillator-sync phase comparator and send- ing its output current I13 (proportional to the phase difference between the two signals) to Pin 15 of the oscillator after it has been filtered properly with an external low-pass circuit. The time constant of the filter can be switched between two values according to the impedance presented by Pin 12. The voltage limiter at the output of the phase comparator limits the voltage excursion on Pin 13 and therefore the frequency range in which the oscillator remains held-in. The output resistance of Pin 13 is: q low when V13 > 4.3 or V13 < 1.6V q high when 1.6V < V13 < 4.3V To prevent the vertical sync from reaching the oscillator-sync phase comparator along with the horizontal sync,a signal which inhibits the phase detector during the vertical interval is taken from the vertical output stage; inhibition remain even if the video signal is not present. The free running frequenc of the oscillator is deter- mined by the values of the capacitor and of the resistor connected to Pins 14 and 15 respectively. To generate the line frequency output pulses, two theresholds are fixed along the fall ramp of the triangular waveform of the oscillator. Pin14 - Oscillator (see Pin 13) Pin 15 - Oscillator control current input (see Pin 13) Pin 16 - Ground TDA1180P 9/12 |
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