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M38K09M3HP Datasheet(PDF) 9 Page - Renesas Technology Corp |
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M38K09M3HP Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 328 page Rev.2.00 Oct 05, 2006 page 5 of 13 38K0 Group REJ09B0337-0200 Fig. 44 Structure of EP00 byte number register ....................................................................... 39 Fig. 45 Structure of EP00 buffer area set register ................................................................... 39 Fig. 46 Structure of EP01 set register ....................................................................................... 40 Fig. 47 Structure of EP01 control register 1 ............................................................................. 40 Fig. 48 Structure of EP01 control register 2 ............................................................................. 41 Fig. 49 Structure of EP01 control register 3 ............................................................................. 41 Fig. 50 Structure of EP01 interrupt source register ................................................................. 41 Fig. 51 Structure of EP01 byte number register 0 ................................................................... 42 Fig. 52 Structure of EP01 byte number register 1 ................................................................... 42 Fig. 53 Structure of EP01 MAX. packet size register .............................................................. 42 Fig. 54 Structure of EP01 buffer area set register ................................................................... 43 Fig. 55 Structure of EP02 set register ....................................................................................... 44 Fig. 56 Structure of EP02 control register 1 ............................................................................. 44 Fig. 57 Structure of EP02 control register 2 ............................................................................. 45 Fig. 58 Structure of EP02 control register 3 ............................................................................. 45 Fig. 59 Structure of EP02 interrupt source register ................................................................. 45 Fig. 60 Structure of EP02 byte number register 0 ................................................................... 46 Fig. 61 Structure of EP02 byte number register 1 ................................................................... 46 Fig. 62 Structure of EP02 MAX. packet size register .............................................................. 46 Fig. 63 Structure of EP02 buffer area set register ................................................................... 47 Fig. 64 Structure of EP03 set register ....................................................................................... 48 Fig. 65 Structure of EP03 control register 1 ............................................................................. 48 Fig. 66 Structure of EP03 control register 2 ............................................................................. 49 Fig. 67 Structure of EP03 control register 3 ............................................................................. 49 Fig. 68 Structure of EP03 interrupt source register ................................................................. 49 Fig. 69 Structure of EP03 byte number register 0 ................................................................... 50 Fig. 70 Structure of EP03 byte number register 1 ................................................................... 50 Fig. 71 Structure of EP03 MAX. packet size register .............................................................. 50 Fig. 72 Structure of EP03 buffer area set register ................................................................... 51 Fig. 73 External bus interface ..................................................................................................... 52 Fig. 74 Data transfer timing of memory channel ...................................................................... 52 Fig. 75 External bus interface (EXB) pin assignment .............................................................. 53 Fig. 76 Block diagram of external bus interface (EXB) ........................................................... 54 Fig. 77 EXB related registers (1) ................................................................................................ 58 Fig. 78 EXB related registers (2) ................................................................................................ 58 Fig. 79 Structure of EXB interrupt source enable register ...................................................... 59 Fig. 80 Structure of EXB interrupt source register ................................................................... 59 Fig. 81 Structure of EXB index register ..................................................................................... 60 Fig. 82 Structure of Register window 1 ..................................................................................... 60 Fig. 83 Structure of Register window 2 ..................................................................................... 60 Fig. 84 Index00[low]; Structure of External I/O configuration register ................................... 61 Fig. 85 Index00[high]; Structure of External I/O configuration register ................................ 61 Fig. 86 Index01[low]; Structure of Transmit/Receive buffer register ...................................... 62 Fig. 87 Index02[low]; Structure of Memory channel operation mode register ...................... 62 Fig. 88 Index03[low]; Structure of Memory address counter .................................................. 62 Fig. 89 Index03[high]; Structure of Memory address counter ................................................. 63 Fig. 90 Index04[low]; Structure of End address register ......................................................... 63 Fig. 91 Index04[high]; Structure of End address register ........................................................ 63 Fig. 92 CPU channel receiving operation .................................................................................. 64 Fig. 93 CPU channel tranmitting operation ................................................................................ 65 Fig. 94 Memory channel receiving operation (1) ...................................................................... 66 Fig. 95 Memory channel receiving operation (2) ...................................................................... 67 List of figures |
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