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M38040FEHHP Datasheet(PDF) 11 Page - Renesas Technology Corp |
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M38040FEHHP Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 387 page vii 3804 Group (Spec.H) List of figures REJ09B0212-0100Z Rev.1.00 Jan 14, 2005 CHAPTER 2 APPLICATION Fig. 2.1.1 Memory map of I/O port relevant registers .............................................................. 2-2 Fig. 2.1.2 Structure of Port Pi (i = 0 to 6) ................................................................................. 2-3 Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6) .................................................. 2-3 Fig. 2.1.4 Structure of Port Pi pull-up control register (i = 0, 1, 2, 4, 5, 6) ......................... 2-4 Fig. 2.1.5 Structure of Port P3 pull-up control register ............................................................ 2-4 Fig. 2.2.1 Memory map of registers relevant to interrupt ........................................................ 2-8 Fig. 2.2.2 Structure of Interrupt source selection register ....................................................... 2-8 Fig. 2.2.3 Structure of Interrupt edge selection register .......................................................... 2-9 Fig. 2.2.4 Structure of Interrupt request register 1 ................................................................... 2-9 Fig. 2.2.5 Structure of Interrupt request register 2 ................................................................. 2-10 Fig. 2.2.6 Structure of Interrupt control register 1 .................................................................. 2-10 Fig. 2.2.7 Structure of Interrupt control register 2 .................................................................. 2-11 Fig. 2.2.8 Interrupt operation diagram ....................................................................................... 2-13 Fig. 2.2.9 Changes of stack pointer and program counter upon acceptance of interrupt request .... 2-14 Fig. 2.2.10 Time up to execution of interrupt processing routine ......................................... 2-15 Fig. 2.2.11 Timing chart after acceptance of interrupt request ............................................. 2-15 Fig. 2.2.12 Interrupt control diagram ......................................................................................... 2-16 Fig. 2.2.13 Example of multiple interrupts ................................................................................ 2-18 Fig. 2.2.14 Sequence of changing relevant register ............................................................... 2-20 Fig. 2.2.15 Sequence of check of interrupt request bit .......................................................... 2-21 Fig. 2.3.1 Memory map of registers relevant to timers .......................................................... 2-22 Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Prescaler Y ............................................ 2-23 Fig. 2.3.3 Structure of Timer 1 .................................................................................................. 2-23 Fig. 2.3.4 Structure of Timer 2, Timer X, Timer Y ................................................................. 2-24 Fig. 2.3.5 Structure of Timer Z (low-order, high-order) .......................................................... 2-24 Fig. 2.3.6 Structure of Timer XY mode register ...................................................................... 2-25 Fig. 2.3.7 Structure of Timer Z mode register ......................................................................... 2-26 Fig. 2.3.8 Structure of Timer 12, X count source selection register .................................... 2-28 Fig. 2.3.9 Structure of Timer Y, Z count source selection register ...................................... 2-28 Fig. 2.3.10 Structure of Interrupt source selection register ................................................... 2-29 Fig. 2.3.11 Structure of Interrupt request register 1 ............................................................... 2-30 Fig. 2.3.12 Structure of Interrupt request register 2 ............................................................... 2-30 Fig. 2.3.13 Structure of Interrupt control register 1 ................................................................ 2-31 Fig. 2.3.14 Structure of Interrupt control register 2 ................................................................ 2-31 Fig. 2.3.15 Timers connection and setting of division ratios ................................................. 2-33 Fig. 2.3.16 Relevant registers setting ....................................................................................... 2-33 Fig. 2.3.17 Control procedure ..................................................................................................... 2-34 Fig. 2.3.18 Peripheral circuit example ....................................................................................... 2-35 Fig. 2.3.19 Timers connection and setting of division ratios ................................................. 2-35 Fig. 2.3.20 Relevant registers setting ....................................................................................... 2-36 Fig. 2.3.21 Control procedure ..................................................................................................... 2-37 Fig. 2.3.22 Judgment method of valid/invalid of input pulses ............................................... 2-38 Fig. 2.3.23 Relevant registers setting ....................................................................................... 2-39 Fig. 2.3.24 Control procedure ..................................................................................................... 2-40 Fig. 2.3.25 Timers connection and setting of division ratios ................................................. 2-41 Fig. 2.3.26 Relevant registers setting ....................................................................................... 2-42 Fig. 2.3.27 Control procedure (1) .............................................................................................. 2-43 Fig. 2.3.28 Control procedure (2) .............................................................................................. 2-44 Fig. 2.4.1 Memory map of registers relevant to Serial I/O .................................................... 2-47 Fig. 2.4.2 Structure of Transmit/Receive buffer register 1 and Transmit/Receive buffer register 3 .. 2-48 |
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