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XIO3130_0808 Datasheet(PDF) 5 Page - Texas Instruments |
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XIO3130_0808 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 139 page  XIO3130 www.ti.com SLLS693D – MAY 2007 – REVISED AUGUST 2008 4.3.43 Next-Item Pointer Register .................................................................................... 104 4.3.44 Subsystem Vendor ID Register .............................................................................. 104 4.3.45 Subsystem ID Register ........................................................................................ 104 4.3.46 PCI Express Capability ID Register ......................................................................... 104 4.3.47 Next-Item Pointer Register .................................................................................... 105 4.3.48 PCI Express Capabilities Register ........................................................................... 105 4.3.49 Device Capabilities Register .................................................................................. 105 4.3.50 Device Control Register ....................................................................................... 106 4.3.51 Device Status Register ........................................................................................ 107 4.3.52 Link Capabilities Register ..................................................................................... 108 4.3.53 Link Control Register .......................................................................................... 109 4.3.54 Link Status Register ........................................................................................... 110 4.3.55 Slot Capabilities Register ..................................................................................... 110 4.3.56 Slot Control Register .......................................................................................... 112 4.3.57 Slot Status Register ............................................................................................ 114 4.3.58 TI Proprietary Register ........................................................................................ 115 4.3.59 TI Proprietary Register ........................................................................................ 115 4.3.60 TI Proprietary Register ........................................................................................ 116 4.3.61 General Control Register ...................................................................................... 116 4.3.62 L0s Idle Timeout Register ..................................................................................... 118 4.3.63 General Slot Info Register .................................................................................... 118 4.3.64 Advanced Error Reporting Capabilities ID Register ....................................................... 119 4.3.65 Next Capability Offset/Capability Version Register ........................................................ 119 4.3.66 Uncorrectable Error Status Register ......................................................................... 119 4.3.67 Uncorrectable Error Mask Register .......................................................................... 120 4.3.68 Uncorrectable Error Severity Register ...................................................................... 121 4.3.69 Correctable Error Status Register ........................................................................... 122 4.3.70 Correctable Error Mask Register ............................................................................. 123 4.3.71 Advanced Error Capabilities and Control Register ........................................................ 123 4.3.72 Header Log Register .......................................................................................... 124 5 PCI Hot Plug Implementation Overview ............................................................................... 125 5.1 PCI Hot Plug Architecture Overview ................................................................................... 125 5.2 PCI Hot Plug Timing ...................................................................................................... 126 5.2.1 Power-Up Cycle ................................................................................................ 126 5.2.1.1 NonPCI Hot Plug Power-Up Cycle ................................................................ 127 5.2.1.2 PCI Hot Plug Power-Up Cycle With PWRGDn Feedback ..................................... 127 5.2.1.3 PCI Hot Plug Power-Up Cycle With No PWRGDn Feedback ................................. 127 5.2.2 Power-Down Cycles ........................................................................................... 128 5.2.2.1 Normal Power-Down ................................................................................ 128 5.2.2.2 Surprise Removal ................................................................................... 129 5.2.2.3 PWRGDn De-Assertion ............................................................................ 129 5.2.3 PMI_Turn_Off and PME_To_Ack Messages ............................................................... 129 5.2.4 Debounce Circuits ............................................................................................. 130 5.2.5 HP_INTX Pin ................................................................................................... 130 6 Electrical Characteristics ................................................................................................... 131 6.1 Absolute Maximum Ratings ............................................................................................. 131 6.2 Recommended Operating Conditions .................................................................................. 131 6.3 PCI Express Differential Transmitter Output Ranges ................................................................ 132 6.4 PCI Express Differential Receiver Input Ranges ..................................................................... 133 6.5 PCI Express Differential Reference Clock Input Ranges ............................................................ 134 6.6 PCI Express Reference Clock Output Requirements ................................................................ 135 6.7 3.3-V I/O Electrical Characteristics ..................................................................................... 136 Contents 5 |
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