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LA72715VA Datasheet(PDF) 8 Page - Sanyo Semicon Device

Part No. LA72715VA
Description  Monolithic Linear IC JPN MTS (Multi Channel Television Sound) Decoder IC
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Maker  SANYO [Sanyo Semicon Device]
Homepage  http://www.ssdc-jp.com/eng/
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LA72715V, 72715VA
No.A0982-8/12
Continued from preceding page.
Pin
No.
Pin Name
DC voltage
AC level
Function
Equivalent Circuit
16
SLAVE ADD
SELECT
17
18
Line Out (R)
terminal
Line Out (L)
terminal
DC : 2.4V
AC : -4.5dBV
Line output pin.
250
Ω 300Ω
50k
50k
2.5pF
2.5pF
PAD
19
VCC5V
20
MTS MODE
OUT
No signal
DC : 2.0V
Detection output for M.T.S. signal.
BILINGUAL
:3.0V
MONO
:2.0V
STEREO
:1.0V
10k
10k
PAD
21
REG FILT
DC : 2.4V
Filter terminal of reference voltage source
10k
10k
10k
500
50k
500
PAD
22
23
24
NC
I
2C BUS Serial Interface Specification
(1) Data Transfer Manual
This IC adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL (serial
clock) and SDA (serial data). At first, set up*1the condition of starting data transfer, and after that, input 8 bit data to
SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit),
and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this IC pull down
the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2data transfer stop
condition, thus the transfer comes to close.
*1 Defined by SCL rise down SDA during ‘H’ period.
*2 Defined by SCL rise up SDA during ‘H’ period.
(2) Transfer Data Format
After transfer start condition, transfers slave address (1000 000*) to SDA terminal, control data, then, stop condition
(See figure 1).
Slave address is made up of 7bits, *38th bit shows the direction of transferring data, if it is ‘L’ takes write mode (As
this IC side, this is input operation mode), and in case of ‘H’ reading mode (As this IC side, this is output operation
mode).
Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be
canceled the transfer dates.
*3 It is called R/W bit.




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