LA72730

PS No.A1059-8/8

SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using

products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition

ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.

products described or contained herein.

SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all

semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or

malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise

to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt

safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not

limited to protective circuits and error prevention circuits for safe design, redundant design, and structural

design.

Upon using the technical information or products described herein, neither warranty nor license shall be granted

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intellctual property rights which has resulted from the use of the technical information and products mentioned

above.

Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed

for volume production.

Any and all information described or contained herein are subject to change without notice due to

product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the

SANYO Semiconductor Co.,Ltd. product that you intend to use.

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Reference

Parameter

Symbol

min

max

unit

LOW level input voltage

VIL

-0.5

1.5

V

HIGH level input voltage

VIH

2.5

5.5

V

LOW level output current

IOL

3.0

mA

SCL clock frequency

fSCL

0

100

kHz

Set-up time for a repeated START condition

tSU : STA

4.7

µs

Hold time START condition. After this period, the first clock pulse is generated

tHD : STA

4.0

µs

LOW period of the SCL clock

tLOW

4.7

µs

Rise time of both SDA and SDL signals

tR

0

1.0

µs

HIGH period of the SCL clock

tHIGH

4.0

µs

Fall time of both SDA and SDL signals

tF

0

1.0

µs

Data hold time

tHD : DAT

0

µs

Data set-up time

tSU : DAT

250

ns

Set-up time for STOP condition

tSU : STO

4.0

µs

BUS free time between a STOP and START condition

tBUF

4.7

µs

Definition of timing

This catalog provides information as of May, 2008. Specifications and information herein are subject

to change without notice.

t HD:STA

t SU:STA

t LOW

t R

t F

t HIGH

t HD:DATA

t SU:DAT

t SU:STO

t BUF

SC L

SD A