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ENA1066A Datasheet(PDF) 8 Page - Sanyo Semicon Device

Part # ENA1066A
Description  CMOS IC 4M-bit (512K횞8) Serial Flash Memory
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Manufacturer  SANYO [Sanyo Semicon Device]
Direct Link  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

ENA1066A Datasheet(HTML) 8 Page - Sanyo Semicon Device

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LE25FU406B
No.A1066-8/22
2. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read (status
register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table 3
Status registers" gives the significance of each bit.
Table 3 Status Registers
Bit
Name
Logic
Function
Power-on Time Information
0
Ready
Bit0
RDY
1
Erase/Program
0
0
Write disabled
Bit1
WEN
1
Write enabled
0
0
Bit2
BP0
1
Nonvolatile information
0
Bit3
BP1
1
Nonvolatile information
0
Bit4
BP2
1
Block protect information
See status register descriptions on BP0, BP1, and BP2.
Nonvolatile information
Bit5
0
Bit6
Reserved bits
0
0
Status register write enabled
Bit7
SRWP
1
Status register write disabled
Nonvolatile information
2-1. Status register read
The contents of the status registers can be read using the status register read command. This command can be executed
even during the following operations.
• Small sector erase, sector erase, chip erase
• Page program
• Status register write
"Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first
to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized
to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by
returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is
continued. The data can be read by the status register read command at any time (even during a program or erase cycle).
Figure 6 Status Register Read
CS
SCK
SI
SO
MSB
MSB
MSB
05h
DATA
DATA
High Impedance
8
3
2
1
0
7
6
5
4
15
23
Mode 3
Mode 0
8CLK
16
DATA


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