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M38044F7KP Datasheet(PDF) 4 Page - Renesas Technology Corp

Part # M38044F7KP
Description  8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
Download  387 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M38044F7KP Datasheet(HTML) 4 Page - Renesas Technology Corp

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BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
q CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
q CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
q CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the notes, and the list of registers.
2. Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:
2: Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
: Bit in which nothing is arranged
Name
Functions
At reset
RW
b
0
1
2
3
4
0
0
0
0
0
5
6
7
0
b0
b1
b2
b3
b4
b5
b6
b7
Contents immediately after reset release
Bit attributes
(Note 1)
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Processor mode bits
Stack page selection bit
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.
”Main clock division ratio selection
bits
Not available
b1
b0
0 : 0 page
1 : 1 page
0 0 :
φ = XIN/2 (High-speed mode)
0 1 :
φ = XIN/8 (Middle-speed mode)
1 0 :
φ = XIN/8 (Middle-speed mode)
1 1 :
φ = XIN (Double-speed mode)
: Bit that is not used for control of the corresponding function
0
Notes 1: Contents immediately after reset release
0 •••••• “0” at reset release
1 •••••• “1” at reset release
Undefined •••••• Undefined or reset release
✻ ••••••Contents determined by option at reset release
R••••••Read
••••••Read enabled
✕••••••Read disabled
W••••••Write
••••••Write enabled
✕ ••••••Write disabled
(Note 2)
CPU mode register (CPUM) [Address : 003B16]
Bits
1
b7 b6
0
3. Supplementary
For details of related development tools and documents, refer to web page “3804 Group” on our website
(http://www.renesas.com/eng/products/mpumcu/8bit/38000/index.html).


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