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ENA1352 Datasheet(PDF) 6 Page - Sanyo Semicon Device

Part # ENA1352
Description  Bi-CMOS IC For Mini Component, receiver 1-chip Tuner IC Incorporating PLL
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Manufacturer  SANYO [Sanyo Semicon Device]
Direct Link  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

ENA1352 Datasheet(HTML) 6 Page - Sanyo Semicon Device

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LV23015T
No.A1352-6/17
Continued from preceding page.
No.
Control/data
Description
Related data
(6)
DO pin
control data
DOC0
DOC1
DOC2
• Data to determine the output of the DO pin.
DOC2
DOC1
DOC0
DO pin state
0
0
0
0
0
0
1
1
0
1
0
1
Open
Low detection of unlock
end-UC (See below)
Open
1
1
1
1
0
0
1
1
0
1
0
1
Open
Low at SD ON
Low at stereo
Open
• Open selected with power ON reset
* IF counter measurement end check
(1) DO pin open automatically when end-UC is set and the IF counter starts (CTE = 0
→1).
(2) DO pin becomes low, enabling check of the counter end when the IF counter measurement is
over.
(3) DO pin open with serial data input/output (CE pin : Hi)
Note)DO pin open regardless of the DO pin control data (DOC0 to 2) during data input period (IN1
and IN2 modes CE-Hi period).
The DO pin state allows output of the content of internal DO serial data in synchronization with
CL regardless of the DO pin control data (DOC0 to 2) during data input period (OUT mode CE :
Hi period).
UL0, UL1
CTE
(7)
Unlock
detection data
UL0, UL1
• Data to select the phase error (φE) detection width to determine if PLL is locked. Unlock is determined
when the phase error exceeding the detection width occurs.
(* : don’t care)
UL1
UL0
φE Detection width
Detection output
0
0
1
0
1
*
Stop
0
±6.67μs
Open
φE output directly
φE extended by 1 to 2ms
* unlock : DO pin becomes Low and the serial data output becomes UL = 0.
DOC0
DOC1
DOC2
(8)
Phase
comparator
control data
DZ0, DZ1
• Data to control the dead band of phase comparator.
DZ1
DZ0
Deadband mode
0
0
1
1
0
1
0
1
DZA
DZB
DZC
DZD
Dead band : DZA < DZB < DZC < DZD
(9)
Output port data
BO1
• Data to determine the output of output ports BO1
“Data” = 0 : OPEN
1 : Low
(10)
Charge pump
control data
DLC
• Data for forced control of the charge pump output
DLC
Charge pump output
0
1
Normal operation
Forced Low
When the VCO control voltage (Vtune) develops dead lock because of stop of oscillation of VCO at
0V, set the charge pump output to LOW and Vtune to VCC to escape the dead lock. (Dead lock
clear circuit)
(11)
IFS
• Normally, set data = 1. Setting the data = 0 causes worsening of the input sensitivity, resulting in decrease
of the sensitivity by about 10 to 30mVrms.
(12)
LSI test data
TEST0 to 2
• LSI test data
TEST0
TEST1
All to be set to “0”
TEST2
All set to 0 for power ON reset
(13)
DNC
• Set data = 0.
Continued on next page.
DO pin
(1) Count start
(2) Count end
(3) CE : HI


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