RENESAS LSIs

262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM

M5M5256DFP,VP -70G,-70GI,-70XG

6

Write cycle ( /S control mode)

(Note 5)

(Note 3)

(Note 3)

(Note 4)

DATA IN

STABLE

/S

/W

Note 3 : Hatching indicates the state is "don't care".

5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.

6 : Don't apply inv erted phase signal externally when DQ pin is output mode.

4 : Writing is executed in ov erlap of /S and /W low.

7 : ten, tdis are periodically sampled and are not 100% tested.

(4) MEASUREMENT CONDITIONS

Input rise and fall time ..... 5ns

Output load ...................... Fig.2, CL=100pF

CL=5pF (for ten,tdis)

T ransition is measured ±500mV from steady

state voltage. (for ten,tdis)

Vcc

DQ

Fig.2 Output load

1.8k

Ω

990

Ω

(Including

scope and JIG)

Limits1:Vcc=3.3±0.3V

Input rise and fall time ..... 5ns

Output load ...................... Fig.1, CL=30pF

CL=5pF (for ten,tdis)

T ransition is measured ±500mV from steady

state voltage. (for ten,tdis)

Limits2:Vcc=5.0±0.5V

DQ

Fig.1 Output load

(Including

scope and JIG)