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MDP1403680KFE04 Datasheet(PDF) 3 Page - Vishay Siliconix |
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MDP1403680KFE04 Datasheet(HTML) 3 Page - Vishay Siliconix |
3 / 5 page www.vishay.com For technical questions contact: ff2aresistors@vishay.com Document Number: 31511 3 Revision: 28-Jul-06 MDP 01, 03, 05 Vishay Dale Thick Film Resistor Networks, Dual-In-Line, Molded DIP, 01, 03, 05 Schematics Standard E-24 resistance values stocked. Consult factory IMPEDANCE CODES CODE R1( Ω) R2( Ω)CODE R1( Ω) R2( Ω) 500B 82 130 141A 270 270 750B 120 200 181A 330 390 800C 130 210 191A 330 470 990A 160 260 221B 330 680 101C 180 240 281B 560 560 111C 180 270 381B 560 1.2K 121B 180 390 501C 620 2.7K 121C 220 270 102A 1.5K 3.3K 131A 220 330 202B 3K 6.2K CIRCUIT APPLICATIONS 01 SCHEMATIC 13 and 15 resistors with one pin common The MDPXX01 circuit provides a choice of 13 and 15 nominally equal resistors, each connected between a common pin (14 and 16) and a discrete PC board pin. Commonly used in the following applications: • MOS/ROM Pull-up/Pull-down • TTL Input Pull-down • Open Collector Pull-up • Digital Pulse Squaring • "Wired OR" Pull-up • TTL Unused Gate Pull-up • Power Driven Pull-up • High Speed Parallel Pull-up 03 SCHEMATIC 7 and 8 isolated resistors The MDPXX03 provides a choice of 7 and 8 nominally equal resistors, each resistor isolated from all others and wired directly across. Commonly used in the following applications: • "Wired OR" Pull-up • Long-line Impedance Balancing • Power Driven Pull-up • LED Current Limiting • Powergate Pull-up • ECL Output Pull-down • Line Termination • TTL Input Pull-down 05 SCHEMATIC TTL dual-line terminator; pulse squaring The MDPXX05 circuit contains 12 and 14 series pair of resistors. Each series pair is connected between ground and a common line. The junction of these resistor pairs is connected to the input terminals. The 05 circuits are designed for TTL dual-line termination and pulse squaring. • • • • • • • • Pin #1 MDP1401 MDP1601 MDP1603 MDP1403 Pin #1 MDP1405, MDP1605 Pin #1 R1 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 R1 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R2 |
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