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Y090312R7560A9B Datasheet(PDF) 2 Page - Vishay Siliconix

Part # Y090312R7560A9B
Description  Bulk Metal® Foil Technology Low Profile Conformally Coated High Precision Resistor with Tight Tolerance from ± 0.01 %
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Manufacturer  VISHAY [Vishay Siliconix]
Direct Link  http://www.vishay.com
Logo VISHAY - Vishay Siliconix

Y090312R7560A9B Datasheet(HTML) 2 Page - Vishay Siliconix

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VSH, VSC
Vishay Foil Resistors Bulk Metal
® Foil Technology Low Profile Conformally Coated High
Precision Resistor with Tight Tolerance from ± 0.01 % and Load
Life Stability of ± 0.01 % and Instantaneous Thermal Stabilization
www.vishay.com
For any questions, contact: foil@vishay.com
Document Number: 63087
2
Revision: 27-Aug-08
TABLE 1 - TOLERANCE AND TCR VS. RESISTANCE VALUE (- 55 °C to + 125 °C, + 25 °C Ref.)
RESISTOR
RESISTANCE VALUE
(
Ω)
TYPICAL TCR AND MAX. SPREAD
(ppm/°C)
TOLERANCE
(%)
VSH2
VSC2
60K to 120K
± 2 ± 4.5
± 0.01 %
VSH1
VSC1
80 to < 60K
± 2 ± 4.5
± 0.01 %
VSH1
VSC1
50 to < 80
± 2 ± 5.5
± 0.02 %
VSH1
VSC1
5 to < 50
± 2 ± 6.5
± 0.05 %
TABLE 2 - PERFORMANCE SPECIFICATIONS
TEST
CONDITIONS
ΔR (%) - TYPICAL
ΔR (%) - MAXIMUM
Moisture Resistance
MIL-STD-202, method 106
± 0.005
± 0.03
Pressure Cooker Test
2 atmospheres absolute pressure,
121 °C, 100 % R.H. for 100 h
± 0.2
± 0.4
Short Time Overload
6.25 x Pnom, 5 s
± 0.005
± 0.05
Resistance to Solder Heat
+ 260 °C, 20 s
± 0.01
± 0.03
Terminal Strength
2 lbs, 10 s
± 0.0025
± 0.03
Insulation Resistance
DC 100 V, 2 min
> 10 000M
> 10 000M
Dielectric Withstanding Voltage
AC 300 V, 1 min
± 0.0025
± 0.03
Thermal Shock
- 65 °C to + 150 °C, 5 cycles
± 0.01
± 0.02
Shock
MIL-STD-202, method 213, condition I
± 0.005
± 0.03
Vibration
MIL-STD-202, method 204, condition D
± 0.01
± 0.03
Load Life Stability
0.3 W, + 70 °C, 2000 h
± 0.01
± 0.015
Thermal EMF
-
0.07 µV/°C
0.1 µV/°C
Current Noise
Quan-Tech
- 42 dB
- 32 dB
Low Temperature Storage
24 h at - 65 °C
± 0.005
± 0.01
Low Temperature Operation
45 min at - 65 °C
± 0.005
± 0.01
High Temperature Exposure
+ 150 °C
± 0.01
± 0.03
FIGURE 2 - TRIMMING TO VALUES
(Conceptual Illustration)
Mutual Inductance
Reduction due
to Change in
Current Direction
Current Path
Before Trimming
Note: Foil shown in black, etched spaces in white
Interloop Capacitance
Reduction in Series
Trimming Process
Removes this Material
from Shorting Strip Area
Changing Current Path
and Increasing
Resistance
Current Path
After Trimming
FIGURE 3 - POWER DERATING CURVE
100
75
50
25
0
- 75
- 50
- 25
0
+ 25
+ 50
+ 75 + 100 + 125 + 150 + 175
Ambient Temperature (°C)
+ 70 °C


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