Electronic Components Datasheet Search |
|
AD5522JSVDZ Datasheet(PDF) 10 Page - Analog Devices |
|
AD5522JSVDZ Datasheet(HTML) 10 Page - Analog Devices |
10 / 60 page AD5522 Rev. A | Page 10 of 60 Parameter Min Typ1 Max Unit Test Conditions/Comments INTERACTION AND CROSSTALK2 DC Crosstalk (FOHx) 0.05 0.65 mV DC change resulting from a dc change in any DAC in the device, FV and FI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ DC Crosstalk (MEASOUTx) 0.05 0.65 mV DC change resulting from a dc change in any DAC in the device, MV and MI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ DC Crosstalk Within a Channel 0.05 mV All channels in FVMI mode, one channel at midscale; measure the current for one channel in the lowest current range for a change in comparator or clamp DAC levels for that PMU SPI INTERFACE LOGIC INPUTS Input High Voltage, VIH 1.7/2.0 V (2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant input levels Input Low Voltage, VIL 0.7/0.8 V (2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant input levels Input Current, IINH, IINL −1 +1 μA Input Capacitance, CIN2 10 pF CMOS LOGIC OUTPUTS SDO, CPOx Output High Voltage, VOH DVCC − 0.4 V Output Low Voltage, VOL 0.4 V IOL = 500 μA. Tristate Leakage Current −2 +2 μA SDO, CPOH1/SDO −1 +1 μA All other output pins Output Capacitance2 10 pF OPEN-DRAIN LOGIC OUTPUTS BUSY, TMPALM, CGALM Output Low Voltage, VOL 0.4 V IOL = 500 μA, CLOAD = 50 pF, RPULLUP = 1 kΩ Output Capacitance2 10 pF LVDS INTERFACE LOGIC INPUTS REDUCED RANGE LINK2 Input Voltage Range 875 1575 mV Input Differential Threshold −100 +100 mV External Termination Resistance 80 100 120 Ω Differential Input Voltage 100 mV LVDS INTERFACE LOGIC OUTPUTS REDUCED RANGE LINK Output Offset Voltage 1200 mV Output Differential Voltage 400 mV POWER SUPPLIES AVDD 10 28 V |AVDD − AVSS| ≤ 33 V AVSS −23 −5 V DVCC 2.3 5.25 V AIDD 26 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled AISS −26 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled AIDD 28 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled AISS −28 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled AIDD 36 mA External range, excluding load conditions AISS −36 mA External range, excluding load conditions DICC 1.5 mA Maximum Power Dissipation2 7 W Maximum power that should be dissipated in this package under worst-case load conditions; careful consideration should be given to supply selection and thermal design |
Similar Part No. - AD5522JSVDZ |
|
Similar Description - AD5522JSVDZ |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |