AD9520-4 datasheet(1/84 Pages) AD

Part #	AD9520-4

Description	12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO

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12 LVPECL/24 CMOS Output Clock

Generator with Integrated 1.6 GHz VCO

AD9520-4

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 1.4 GHz to 1.8 GHz

Supports external 0 V to 5 V VCO/VCXO to 2.4 GHz

1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz

Accepts 16.67 MHz to 33.3 MHz crystal for reference input

Optional reference clock doubler

Reference monitoring capability

Auto and manual reference switchover/holdover modes,

with selectable revertive/nonrevertive switching

Glitch-free switchover between references

Automatic recover from holdover

Digital or analog lock detect, selectable

Optional zero delay operation

Twelve 1.6 GHz LVPECL outputs divided into 4 groups

Each group of 4 has a 1-to-32 divider with phase delay

Additive output jitter as low as 225 fS rms

Channel-to-channel skew grouped outputs <16 ps

Each LVPECL output can be configured as two CMOS

outputs (for fOUT ≤ 250 MHz)

Automatic synchronization of all outputs on power-up

Manual synchronization of outputs as needed

SPI- and I²C-compatible serial control port

64-lead LFCSP

Nonvolatile EEPROM stores configuration settings

APPLICATIONS

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC,

and other 10 Gbps protocols

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

ATE and high performance instrumentation

Broadband infrastructures

GENERAL DESCRIPTION

The AD9520-41 provides a multioutput clock distribution

function with subpicosecond jitter performance, along with an

on-chip PLL and VCO. The on-chip VCO tunes from 1.4 GHz to

1.8 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz

can also be used.

FUNCTIONAL BLOCK DIAGRAM

OPTIONAL

REF1

REF2

CLK

LF

DIVIDER

AND MUXs

ZERO

DELAY

CP

VCO

STATUS

MONITOR

SPI/I2C CONTROL

PORT AND

DIGITAL LOGIC

EEPROM

AD9520

OUT0

OUT1

OUT2

DIV/Φ

OUT3

OUT4

OUT5

DIV/Φ

OUT6

OUT7

OUT8

DIV/Φ

OUT9

OUT10

OUT11

DIV/Φ

LVPECL/

CMOS

REFIN

Figure 1.

The AD9520 serial interface supports both SPI and I2C® ports.

An in-package EEPROM can be programmed through the serial

interface and store user-defined register setting for power-up

and chip reset.

The AD9520 features 12 LVPECL outputs in four groups. Any

of the 1.6 GHz LVPECL outputs can be reconfigured as two

250 MHz CMOS outputs.

Each group of outputs has a divider that allows both the divide

ratio (from 1 to 32) and phase (coarse delay) to be set.

The AD9520 is available in a 64-lead LFCSP and can be operated

from a single 3.3 V supply. The external VCO can have an

operating voltage up to 5.5 V. A separate output driver power

supply can be from 2.375 V to 3.465 V.

The AD9520 is specified for operation over the standard industrial

range of −40°C to +85°C.

1 The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-4 is used, it is referring to that specific

member of the AD9520 family.

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