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MC44S803EP Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MC44S803EP Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 36 page  Freescale Semiconductor 11 MC44S803 INTER-IC (I2C) INTERFACE TIMING Figure 6. I2C Timing Diagram Table 11. I2C Interface Bus Specifications Parameter Symbol Min. Max. Units Low Level Output Voltage VDD > 2.0 V VDD < 2.0 V VOL 0 0 0.4 0.2 VDD V High Level Input Voltage VIH 0.7 VDD VDDmax+0.5 V Low Level Input Voltage VIL –0.5 0.3 VDD V Absolute Max Input Voltage — — 5.0 V Hysteresis of Schmitt Trigger Inputs VDD > 2.0 V VDD < 2.0 V Vhys 0.05 VDD 0.1 VDD — — V Capacitance for each I/O Pin(1) 1. Cb = total capacitance of one bus line in pF. Cin — 10 pF Pulse Width of Spikes Filtered Out tSP 0 50 nS SCLK Frequency fSCLK 0 800 kHz Hold Time Start Condition tHD;STA 500 — ns Set-Up Time for Repeated Start tSU;STA 500 — ns Data Set-Up Time tSU;DAT 100 — ns Data Hold Time tHD;DAT 0 — ns Set-Up Time for Stop Condition tSU;STO 500 — ns Low Period of the SCLK Clock tLOW 0.6 — µs High Period of the SCLK Clock tHIGH 0.6 — µs Rise Time of both SDA and SCLK tr 20 + 0.1Cb 300 ns Fall Time of both SDA and SCLK tf 20 + 0.1Cb 300 ns Bus Free Time between Stop and Start tBUF 200 — ns SDA Sample SCLK tHD;STA tf tr tLOW tHIGH AD7 AD1 R19 R12 0 R11 R4 R3 R0 A3 A0 Slave Ack tBUF Control Byte 2 IC Address R/W Control Byte 1 Ctrl Nibble 0 Reg Addr S P S tSU;DAT tHD;DAT tSU;STO Stop Condition Start Condition MSB LSB Master Writes to Slave Input SDA SCLK tSP AD7 AD1 D19 D12 1 D11 D4 D3 D0 1 0 Master Not Ack Data Byte 2 IC Address R/W Data Byte 1 Data Nibble 0 1 S P Stop Condition Start Condition MSB LSB Master Reads from Slave 10 0 There is a maximum of 20 data bits, the rest are fixed Slave Ack Slave Ack Slave Ack Slave Ack Master Ack Master Ack |
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Similar Description - MC44S803EP |
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