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TS5070FNTR Datasheet(PDF) 10 Page - STMicroelectronics |
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TS5070FNTR Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 32 page This mode provides another stage of path verifica- tion by enabling data written into the Receive PCM Register to be read back from that register in any Transmit time-slot at DX0or DX1. For Analog Loopback as well as for Digital Loop- back PCM decoding continues and analog output appears at VFRO. The output can be disabled by pro gramming ”No Output” in the Receive Gain Register (see table 8). INTERFACE LATCH DIRECTIONS Immediately following power-on, all Interface Latches assume they are inputs, and therefore all IL pins are in a high impedance state. Each IL pin may be individually programmed as a logic input or output by writing the appropriate instruction to the LDR, see table 1 and 4. Bits L5-L0 must be set by writing the specific instruction to the LDR with the L bits in the second byte set as specified in table 4. Unused interface latches should be programmed as outputs. For the TS5071, L5 should always be programmed as an output. (*) State at power-on initilization. Note: L5 should be programmed as an output for the TS5071. INTERFACE LATCH STATES Interface Latches configured as outputs assume the state determined by the appropriate data bit in the 2-byte instruction written to the Latch Content Register (ILR) as shown in tables 1 and 5. Latches configured as inputs will sense the state applied by an external source, such as the Off- Hook detect output of a SLIC. All bits of the ILR, i.e. sensed inputs and the programmed state of outputs, can be read back in the 2nd byte of a READ from the ILR. It is recommended that, dur- ing initialization, the state of IL pins to be config- ured as outputs should first be programmed, fol- lowed immediately by the Latch Direction Register. TIME-SLOT ASSIGNMENT COMBO IIG can operate in either fixed time-slot or time-slot assignment mode for selecting the Trans- mit and Receive PCM time-slots. Following power- on, the deviceis automaticallyin Non-Delayed Tim- ing mode, in which the time-slot always begins with the leading (rising) edge of frame sync inputs FSX and FSR. Time-Slot Assignment may only be used with Delayed Data timing : see figure 6. FSX and FSR may have any phase relationship with each other in BCLK period increments. Bit Number 765 43 210 L0 L1 L2 L3 L4 L5 X X Table 4: Byte 2 Function of Latch Direction Register LN Bit IL Direction 0 1 Input * Output Bit Number Function 7 EN 6 PS (note 1) 5 T5 (note 2) 4 T4 3 T3 2 T2 1 T1 0 T0 0 X X XXXXX Disable DX Outputs (transmit instruction) * Disable DR Inputs (receive instruction) * 10 Assign One Binary Coded Time-slot from 0–63 Assign One Binary Coded Time-slot from 0–63 Enable DX0 Output, Disable DX1 Output (Transmit instruction) Enable DR0 Input, Disable DR1 Input (Receive Instruction) 11 Assign One Binary Coded Time-slot from 0–63 Assign One Binary Coded Time-slot from 0–63 Enable DX1 Output, Disable DX0 Output (Transmit instruction) Enable DR1 Input, Disable DR0 Input (Receive Instruction) Table 6: Byte 2 of Time-slot and Port Assignment Instructions Bit Number 7654 32 10 D0 D1 D2 D3 D4 D5 X X Table 5: Interface Latch Data Bit Order Notes: 1. The ”PS” bit MUST always be set to 0 for the TS5071. 2. T5 is the MSB of the time-slot assignment. (*) State at power-on initialization TS5070 - TS5071 10/32 |
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