ABRIDGED DATA SHEET

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108

Rev: 101708

10 of 13

7 Pin Descriptions

7.1 Short Pin Descriptions

Table 7-1. Short Pin Descriptions

PIN NAME

TYPE

PIN DESCRIPTION

TDM Interface

TDMn_ACLK

O

TDMoP Recovered Clock Output

TDMn_TCLK

Ipu

TDMoP Transmit Clock Input (here transmit means “away from Ethernet MII”)

TDMn_TX

O

TDMoP Transmit Data Output

TDMn_TX_SYNC

Ipd

TDMoP Transmit Frame Sync Input

TDMn_TX_MF_CD

IOpd

TDMoP Transmit Multiframe Sync Input or Carrier Detect Output

TDMn_TSIG_CTS

O

TDMoP Transmit Signaling Output or Clear to Send Output

TDMn_RCLK

Ipu

TDMoP Receive Clock Input (here receive means “toward Ethernet MII”)

TDMn_RX

Ipu

TDMoP Receive Data Input

TDMn_RX_SYNC

Ipd

TDMoP Receive Frame/Multiframe Sync Input

TDMn_RSIG_RTS

Ipu

TDMoP Receive Signaling Input or Request To Send Input

SDRAM Interface

SD_CLK

O

SDRAM Clock

SD_D[31:0]

IO

SDRAM Data Bus

SD_DQM[3:0]

O

SDRAM Byte Enable Mask

SD_A[11:0]

O

SDRAM Address Bus

SD_BA[1:0]

O

SDRAM Bank Select Outputs

SD_CS_N

O

SDRAM Chip Select (Active Low)

SD_WE_N

O

SDRAM Write Enable (Active Low)

SD_RAS_N

O

SDRAM Row Address Strobe (Active Low)

SD_CAS_N

O

SDRAM Column Address Strobe (Active Low)

Ethernet PHY Interface (MII/RMII/SSMII)

CLK_MII_TX

I

MII Transmit Clock Input

CLK_SSMII_TX

O

SSMII Transmit Clock Output

MII_TXD[3:0]

O

MII Transmit Data Outputs

MII_TX_EN

O

MII Transmit Enable Output

MII_TX_ERR

O

MII Transmit Error Output

CLK_MII_RX

I

MII Receive Clock Input

MII_RXD[3:0]

I

MII Receive Data Inputs

MII_RX_DV

I

MII Receive Data Valid Input

MII_RX_ERR

I

MII Receive Error Input

MII_COL

I

MII Collision Input

MII_CRS

I

MII Carrier Sense Input

MDC

O

PHY Management Clock Output

MDIO

IOpu

PHY Management Data Input/Output

Global Clocks

CLK_SYS_S

I

System Clock Selection Input

CLK_SYS

I

System Clock Input: 25, 50 or 75MHz

CLK_CMN

I

Common Clock Input (for common clock mode also known as differential mode)

CLK_HIGH

I

Clock High Input (for adaptive clock recovery machines and E1/T1 master clocks)

CPU Interface

H_CPU_SPI_N

Ipu

Host Bus Interface (1=Parallel Bus, 0=SPI Bus)

DAT_32_16_N

Ipu

Data Bus Width (1=32-bit , 0=16-bit)

H_D[31:1]

IO

Host Data Bus

H_D[0] / SPI_MISO

IO

Host Data LSb or SPI Data Output

H_AD[24:1]

I

Host Address Bus

H_CS_N

I

Host Chip Select (Active Low)

H_R_W_N / SPI_CP

I

Host Read/Write Control or SPI Clock Phase

H_WR_BE0_N / SPI_CLK

I

Host Write Enable Byte 0 (Active Low) or SPI Clock

H_WR_BE1_N / SPI_MOSI

I

Host Write Enable Byte 1 (Active Low) or SPI Data Input