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ADS7865IPBSR Datasheet(PDF) 8 Page - Texas Instruments |
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ADS7865IPBSR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 30 page TIMING REQUIREMENTS (1) CLOCK CONVST 10ns Cyc e l 1 Cyc e l 2 A B C 10ns 5ns 5ns ADS7865 SBAS441 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com ADS7865 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tCONV Conversion time fCLOCK = 32MHz 13 tCLK tACQ Acquisition time 62.5 ns fCLK CLOCK frequency 1 32 MHz tCLK CLOCK period 31.25 1000 ns tCLKL CLOCK low time 9.4 ns tCLKH CLOCK high time 9.4 ns t1 CONVST low time 20 ns CONVST falling edge to BUSY high t2 3 ns delay(2) t3 CONVST high time 20 ns t4 RD falling edge to BUSY high setup time 1 tCLK t5 14th CLOCK rising edge to BUSY low delay 3 ns See Figure 1 CS falling edge to RD or WR falling edge t6 0 ns setup time CS rising edge to RD or WR rising edge t7 0 ns hold time t8 WR low time 10 ns t9 RD high time between two read accesses 10 ns t10 RD falling edge to output data valid delay 20 ns t11 Output data hold time 5 ns t12 Input data setup time 10 ns t13 Input data hold time 5 ns Input data still valid to CONVST falling edge t14 31.25 ns setup time (1) All input signals are specified with tR = tF = 1.5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Not applicable in auto-Nap power-down mode. NOTE: All CONVST commands that occur more than 10ns before the rising edge of cycle '1' of the external clock (Region 'A') initiate a conversion on the rising edge of cycle '1'. All CONVST commands that occur 5ns after the rising edge of cycle '1' or 10ns before the rising edge of cycle '2' (Region 'B') initiate a conversion on the rising edge of cycle '2'. All CONVST commands that occur 5ns after the rising edge of cycle '2' (Region 'C') initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from LOW to HIGH in the region 10ns before the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or the following edge. Figure 2. CONVST Timing 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7865 |
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