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DS32506N Datasheet(PDF) 11 Page - Maxim Integrated Products |
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DS32506N Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 130 page DS32506/DS32508/DS32512 11 of 130 5. DETAILED FEATURES 5.1 Global Features Three interface modes: hardware, 8-/16-bit parallel bus, and SPI serial bus Independent per-port operation (e.g., line rate, jitter attenuator placement, or loopback type) Clock, data, and control signals can be inverted to allow a glueless interface to other devices Manual or automatic one-second update of performance monitoring counters Each port can be put into a low-power standby mode when not being used Requires only a single reference clock for all three LIU data rates using internal clock rate adapter Jitter attenuators can be used in either transmit or receive path Detection of loss-of-transmit clock Two programmable I/O pins per port Optional global write mode configures all LIUs at the same time Glueless interface to neighboring framer and mapper components 5.2 Receiver AGC/equalizer block handles from 0 to 22dB of cable loss Programmable internal termination resistor Loss-of-lock (LOL) PLL status indication Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp Digital and analog loss-of-signal (LOS) detectors (compliant with ANSI T1.231 and ITU G.775) Software programmable B3ZS/HDB3 or AMI decoding Detection and accumulation of bipolar violations (BPV), code violations (CV), and excessive zeros occurrences (EXZ) Detection of receipt of B3ZS/HDB3 codewords Binary or bipolar framer interface On-board programmable PRBS detector Per-channel power-down control 5.3 Transmitter Standards-compliant waveshaping Programmable waveshaping Programmable internal termination resistor Binary or bipolar framer interface Gapped clock capable up to 78MHz with jitter attenuator in transmit path Wide 50 ±20% transmit clock duty cycle Transmit common clock option Software programmable B3ZS/HDB3 or AMI decoding Programmable insertion of bipolar violations (BPV), code violations (CV), and excessive zeros (EXZ) AIS generator: unframed all ones, framed DS3 AIS, and STS-1 AIS-L Line build-out (LBO) control High-impedance line-driver output mode to support protection-switching applications Per-channel power-down control Output driver monitor 5.4 Jitter Attenuator One jitter attenuator per port Fully integrated, requires no external components Meets all applicable ANSI, ITU, ETSI, and Telcordia jitter transfer and output jitter requirements Can be placed in the transmit path, receive path or disabled Programmable FIFO depth: 16, 32, 64, or 128 bits Overflow and underflow status indications |
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