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MAX11014BGTM+ Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX11014BGTM+ Datasheet(HTML) 9 Page - Maxim Integrated Products |
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9 / 70 page  Automatic RF MESFET Amplifier Drain-Current Controllers _______________________________________________________________________________________ 9 Note 1: All current-sense amplifier specifications are tested after a current-sense calibration (valid when drain current = 0mA). See RCS Error vs. GATE Current in the Typical Operating Characteristics. The calibration is valid only at one temperature and supply voltage and must be repeated if either the temperature or supply voltage changes. Note 2: The hardware configuration register’s CH_OCM1 and CH_OCM0 bits are set to 0. See Table 10a. The max specification is limited by tester limitations. Note 3: Guaranteed by design. Not production tested. Note 4: At power-on reset, the output safe switch is closed. See the ALMHCFG (Read/Write) section. Note 5: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset errors have been calibrated out. Note 6: Offset nulled. Note 7: Absolute range for analog inputs is from 0 to VAVDD. Note 8: Device and sensor at the same temperature. Verified by the current ratio (see the Temperature Measurements section). Note 9: All timing specifications referred to VIH or VIL levels. Note 10: DOUT goes into tri-state mode after the CS rising edge. Keep CS low long enough for the DOUT value to be sampled before it goes to tri-state. Note 11: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL’s falling edge. Note 12: tR and tF measured between 0.3 x DVDD and 0.7 x DVDD. Note 13: CB = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be linearly interpolated. Note 14: An appropriate bus pullup resistance must be selected depending on board capacitance. For more information, refer to the I2C documentation on the Philips website. Note 15: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Note 16: When a command is written to the serial interface, it is passed to the internal oscillator clock to be executed. There is a small synchronization delay before the new value is written to the appropriate register. If the user attempts to read the new value back before tRDBK, no harm will be caused to the data, but the read command may not yet show the new value. Note 17: This is the minimum time from the end of a command before CNVST should be asserted. The time allows for the data from the preceding write to arrive and set up the chip in preparation for the CNVST. The time need only be observed when the write affects the ADC controls. Failure to observe this time may lead to incorrect conversions (for example, conversion of the wrong ADC channel). MISCELLANEOUS TIMING CHARACTERISTICS (continued) |
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