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MCIMX351AVM5B Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MCIMX351AVM5B Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
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6 / 140 page  MCIMX35 (i.MX35) Multimedia Applications Processor for Automotive Products Advance Information, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 6 The ARM11 core is intended to operate at a maximum frequency of 532 MHz to support the required multimedia use cases. Furthermore, an Image Processing Unit (IPU) is integrated into the AP domain to offload the ARM11 core from performing functions such as color space conversion, image rotation and scaling, graphics overlay, and pre- and post-processing. Peripheral functionality belonging to the AP domain include the user interface, connectivity, display, security, and memory interfaces and 128 Kbytes of multipurpose SRAM. 2.2 Shared Domain Overview The shared domain is composed of the shared peripherals, a Smart DMA Engine (SDMA) and a number of miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the SDMA engine. The MCIMX35 has a hierarchical memory architecture including L1 caches and unified L2 cache. This reduces the bandwidth demands for the external bus and external memory. The external memory subsystem supports a flexible external memory system, including support for SDRAM (SDR, DDR2 and Mobile DDR) and NAND Flash. 2.3 Advanced Power Management Overview To address the continuing need to reduce power consumption, the following techniques are incorporated in the MCIMX35: • Clock gating • Power gating • Power optimized synthesis • Well biasing The insertion of gating into the clock paths allows unused portions of the chip to be disabled. Since static CMOS logic consumes only leakage power, significant power savings can be realized. “Well biasing” is applying a voltage that is greater than Vdd to the nwells and lower than Vss to the pwells. The effect of applying this well back bias voltage reduces the subthreshold channel leakage. For the 90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten over the nominal leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to 1.22 V. 2.4 ARM11 Microprocessor Core The CPU of the i.MX35 is the ARM1136JF-S core, based on the ARM v6 architecture. This core supports the ARM Thumb® instruction sets, features Jazelle® technology (which enables direct execution of Java byte codes), and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers. The ARM1136JF-S processor core features are as follows: • Integer unit with integral EmbeddedICE™ logic • Eight-stage pipeline • Branch prediction with return stack |
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