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MAX19517 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX19517 Datasheet(HTML) 6 Page - Maxim Integrated Products |
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6 / 35 page  Dual-Channel, 10-Bit, 130Msps ADC 6 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) (VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 130MHz, AIN = -0.5dBFS, data output termina- tion = 50 Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER-MANAGEMENT CHARACTERISTICS Wake-Up Time from Shutdown tWAKE Internal reference, CREFIO = 0.1µF (10 τ)5 ms Wake-Up Time from Standby tWAKE Internal reference 15 µs SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7) SCLK Period tSCLK 50 ns SCLK to CS Setup Time tCSS 10 ns SCLK to CS Hold Time tCSH 10 ns SDIN to SCLK Setup Time tSDS Serial-data write 10 ns SDIN to SCLK Hold Time tSDH Serial-data write 0 ns SCLK to SDIN Output Data Delay tSDD Serial-data read 10 ns TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9), (Default Timing see Table 5) Clock Pulse-Width High tCH 3.85 ns Clock Pulse-Width Low tCL 3.85 ns Clock Duty Cycle tCH/tCLK 30 to 70 % CL = 10pF, VOVDD = 1.8V (Note 2) 9.7 12.2 14.7 Data Delay After Rising Edge of CLK+ tDD CL = 10pF, VOVDD = 3.3V 11.0 ns Data to DCLK Setup Time tSETUP CL = 10pF, VOVDD = 1.8V (Note 2) 5.9 6.7 ns Data to DCLK Hold Time tHOLD CL = 10pF, VOVDD = 1.8V (Note 2) 0.5 0.9 ns TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10), (Default Timing see Table 5) Clock Pulse-Width High tCH 3.85 ns Clock Pulse-Width Low tCL 3.85 ns Clock Duty Cycle tCH/tCLK 30 to 70 % CL = 10pF, VOVDD = 1.8V (Note 2) 6.0 8.3 11.0 Data Delay After Rising Edge of CLK+ tDD CL = 10pF, VOVDD = 3.3V 7.6 ns Data to DCLK Setup Time tSETUP CL = 10pF, VOVDD = 1.8V (Note 2) 0.7 2.4 ns Data to DCLK Hold Time tHOLD CL = 10pF, VOVDD = 1.8V (Note 2) 0.4 1.5 ns DCLK Duty Cycle tDCH/tCLK CL = 10pF, VOVDD = 1.8V (Note 2) 30 50 63 % MUX Data Duty Cycle tCHA/tCLK CL = 10pF, VOVDD = 1.8V (Note 2) 38 50 75 % TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12) Setup Time for Valid Clock Edge tSUV Edge mode (Note 2) 0.7 ns Hold-Off Time for Invalid Clock Edge tHO Edge mode (Note 2) 0.5 ns Minimum Synchronization Pulse Width Relative to input clock period 2 Cycles |
Similar Part No. - MAX19517 |
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Similar Description - MAX19517 |
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