CY2DP814
1:4 Clock Fanout Buffer
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07060 Rev. *E
Revised October 22, 2008
Features
■ Low-voltage operation
■ VDD = 3.3V
■ 1:4 fanout
■ Single input configurable for LVDS, LVPECL, or LVTTL
■ Four differential pairs of LVPECL outputs
■ Drives 50-ohm load
■ Low input capacitance
■ Less than 4 ns typical propagation delay
■ 85 ps typical output-to-output skew
■ Industrial versions available
■ Available in TSSOP package
Description
The Cypress CY2 series of network circuits are produced
using advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DP814 fanout buffer features a single LVDS-
or a single LVPECL-compatible input and four LVPECL output
pairs.
Designed for data communications clock management appli-
cations, the fanout from a single input reduces loading on the
input clock.
The CY2DP814 is ideal for both level translations from
single-ended to LVPECL, and/or for the distribution of
LVDS-based clock signals. The Cypress CY2DP814 has
configurable input between logic families. The input can be
selectable for an LVPECL, LVTTL or LVDS signal, while the
output drivers support LVPECL capable of driving 50-ohm
lines.
Logic Block Diagram
OUTPUT
IN+ 6
IN- 7
16 Q1A
15 Q1B
14 Q2A
13 Q2B
10 Q4A
9 Q4B
12 Q3A
11 Q3B
LVDS /
LVPECL /
LVTTL
CONFIG 2
EN1 1
EN2 8
LVPECL
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