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MPC5565MVZ112R Datasheet(PDF) 11 Page - Freescale Semiconductor, Inc |
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MPC5565MVZ112R Datasheet(HTML) 11 Page - Freescale Semiconductor, Inc |
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11 / 54 page  Electrical Characteristics MPC5565 Microcontroller Data Sheet, Rev. 2.0 Freescale Semiconductor 11 When powering down, VRC33 and VDDSYN have no delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. When not powering up or down, no delta between VRC33 and VDDSYN is required for the VRC to operate within specification. There are no power up/down sequencing requirements to prevent issues such as latch-up, excessive current spikes, and so on. Therefore, the state of the I/O pins during power up and power down varies depending on which supplies are powered. Table 7 gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type). Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and pad_sh (slow type). The values in Table 7 and Table 8 do not include the effect of the weak-pull devices on the output pins during power up. Before exiting the internal POR state, the pins go to a high-impedance state until POR negates. When the internal POR negates, the functional state of the signal during reset applies and the weak-pull devices (up or down) are enabled as defined in the device reference manual. If VDD is too low to correctly propagate the logic signals, the weak-pull devices can pull the signals to VDDE and VDDEH. To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time required to enable the external circuitry connected to the device outputs. Table 7. Pin Status for Fast Pads During the Power Sequence VDDE VDD33 VDD POR Pin Status for Fast Pad Output Driver pad_fc (fast) Low — — Asserted Low VDDE Low Low Asserted High VDDE Low VDD Asserted High VDDE VDD33 Low Asserted High impedance (Hi-Z) VDDE VDD33 VDD Asserted Hi-Z VDDE VDD33 VDD Negated Functional Table 8. Pin Status for Medium and Slow Pads During the Power Sequence VDDEH VDD POR Pin Status for Medium and Slow Pad Output Driver pad_mh (medium) pad_sh (slow) Low — Asserted Low VDDEH Low Asserted High impedance (Hi-Z) VDDEH VDD Asserted Hi-Z VDDEH VDD Negated Functional |
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