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SPC5565MVZ132 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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SPC5565MVZ132 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 54 page  MPC5565 Microcontroller Data Sheet, Rev. 2.0 Electrical Characteristics Freescale Semiconductor 10 3.7 Power-Up/Down Sequencing Power sequencing between the 1.5 V power supply and VDDSYN or the RESET power supplies is required if using an external 1.5 V power supply with VRC33 tied to ground (GND). To avoid power-sequencing, VRC33 must be powered up within the specified operating range, even if the on-chip voltage regulator controller is not used. Refer to Section 3.7.2, “Power-Up Sequence (VRC33 Grounded),” and Section 3.7.3, “Power-Down Sequence (VRC33 Grounded).” Power sequencing requires that VDD33 must reach a certain voltage where the values are read as ones before the POR signal negates. Refer to Section 3.7.1, “Input Value of Pins During POR Dependent on VDD33.” Although power sequencing is not required between VRC33 and VDDSYN during power up, VRC33 must not lead VDDSYN by more than 600 mV or lag by more than 100 mV for the VRC stage turn-on to operate within specification. Higher spikes in the emitter current of the pass transistor occur if VRC33 leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on the board power supply circuitry and the amount of board level capacitance. Furthermore, when all of the PORs negate, the system clock starts to toggle, adding another large increase of the current consumed by VRC33. If VRC33 lags VDDSYN by more than 100 mV, the increase in current consumed can drop VDD low enough to assert the 1.5 V POR again. Oscillations are possible when the 1.5 V POR asserts and stops the system clock, causing the voltage on VDD to rise until the 1.5 V POR negates again. All oscillations stop when VRC33 is powered sufficiently. 9 Absolute value of slew rate on power supply pins — — 50 V/ms 10 Required gain at Tj: IDD ÷ IVRCCTL (@ fsys = fMAX) 6, 7, 8, 9 – 40o C BETA10 40 — — 25o C45 — — 150o C 55 500 — 1 The internal POR signals are V POR15, VPOR33, and VPOR5. On power up, assert RESET before the internal POR negates. RESET must remain asserted until the power supplies are within the operating conditions as specified in Table 9 DC Electrical Specifications. On power down, assert RESET before any power supplies fall outside the operating conditions and until the internal POR asserts. 2 V IL_S (Table 9, Spec15) is guaranteed to scale with VDDEH6 down to VPOR5. 3 Supply full operating current for the 1.5 V supply when the 3.3 V supply reaches this range. 4 It is possible to reach the current limit during ramp up—do not treat this event as short circuit current. 5 At peak current for device. 6 Requires compliance with Freescale’s recommended board requirements and transistor recommendations. Board signal traces/routing from the VRCCTL package signal to the base of the external pass transistor and between the emitter of the pass transistor to the VDD package signals must have a maximum of 100 nH inductance and minimal resistance (less than 1 Ω). V RCCTL must have a nominal 1 μF phase compensation capacitor to ground. VDD must have a 20 μF (nominal) bulk capacitor (greater than 4 μF over all conditions, including lifetime). Place high-frequency bypass capacitors consisting of eight 0.01 μF, two 0.1 μF, and one 1 μF capacitors around the package on the V DD supply signals. 7 I VRCCTL is measured at the following conditions: VDD = 1.35 V, VRC33 = 3.1 V, VVRCCTL = 2.2 V. 8 Refer to Table 1 for the maximum operating frequency. 9 Values are based on I DD from high-use applications as explained in the IDD Electrical Specification. 10 BETA is the worst-case external transistor BETA. It is measured on a per-part basis and calculated as (I DD ÷ IVRCCTL). Table 6. VRC and POR Electrical Specifications (continued) Spec Characteristic Symbol Min. Max. Units |
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