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MC8640DTHX1000H Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc |
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MC8640DTHX1000H Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc |
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4 / 140 page  MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 4 Freescale Semiconductor Overview • DDR memory controllers — Dual 64-bit memory controllers (72-bit with ECC) — Support of up to a 266 MHz clock rate and a 533 MHz DDR2 SDRAM — Support for DDR, DDR2 SDRAM — Up to 16 Gbytes per memory controller — Cache line and page interleaving between memory controllers. • Serial RapidIO interface unit — Supports RapidIO Interconnect Specification, Revision 1.2 — Both 1x and 4x LP-Serial link interfaces — Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) per lane — RapidIO–compliant message unit — RapidIO atomic transactions to the memory controller • PCI Express interface — PCI Express 1.0a compatible — Supports x1, x2, x4, and x8 link widths — 2.5 Gbaud, 2.0 Gbps lane • Four enhanced three-speed Ethernet controllers (eTSECs) — Three-speed support (10/100/1000 Mbps) — Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers — Support of the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI — Support a full-duplex FIFO mode for high-efficiency ASIC connectivity — TCP/IP off-load — Header parsing — Quality of service support — VLAN insertion and deletion — MAC address recognition — Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III programming models — RMON statistics support — MII management interface for control and status • Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts and 48 internal interrupts — Eight global high resolution timers/counters that can generate interrupts — Allows processors to interrupt each other with 32b messages |
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