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MPC8313CVRAFDB Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MPC8313CVRAFDB Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
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2 / 100 page  MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1 2 Freescale Semiconductor Overview 1Overview The MPC8313E incorporates the e300c3 core, which includes 16 Kbytes of L1 instruction and data caches and on-chip memory management units (MMUs). The MPC8313E has interfaces to dual enhanced three-speed 10/100/1000 Mbps Ethernet controllers, a DDR1/DDR2 SDRAM memory controller, an enhanced local bus controller, a 32-bit PCI controller, a dedicated security engine, a USB 2.0 dual-role controller and an on-chip full-speed PHY, a programmable interrupt controller, dual I2C controllers, a 4-channel DMA controller, and a general-purpose I/O port. A block diagram of the MPC8313E is shown in Figure 1. Figure 1. MPC8313E Block Diagram The MPC8313E security engine (SEC 2.2) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. 1.1 MPC8313E Features The following features are supported in the MPC8313E: • Embedded PowerPC™ e300 processor core built on Power Architecture™ technology; operates at up to 333 MHz. • High-performance, low-power, and cost-effective host processor • DDR1/DDR2 memory controller—one 16-/32-bit interface at up to 333 MHz supporting both DDR1 and DDR2 • 16-Kbyte instruction cache and 16-Kbyte data cache, a floating point unit, and two integer units • Peripheral interfaces such as 32-bit PCI interface with up to 66-MHz operation, 16-bit enhanced local bus interface with up to 66-MHz operation, and USB 2.0 (full speed) with an on-chip PHY. • Security engine provides acceleration for control and data plane security protocols • Power management controller for low-power consumption • High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration 16-KB D-Cache 16-KB I-Cache e300c3 Core w/FPU and DUART Interrupt Dual I2C Timers GPIO Local Bus, DDR1/DDR2 Controller Controller DMA PCI I/O Sequencer (IOS) Security Engine 2.2 Note: The MPC8313 does not include a security engine. Power Management SPI USB 2.0 Host/Device/OTG ULPI Gb Ethernet MAC On-Chip FS PHY Gb Ethernet MAC |
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