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MC8641VU1250J Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MC8641VU1250J Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 140 page  MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 1 10 Freescale Semiconductor Electrical Characteristics Table 3. Output Drive Capability Driver Type Programmable Output Impedance ( Ω) Supply Voltage Notes DDR1 signal 18 36 (half strength mode) D n_GVDD = 2.5 V 4, 9 DDR2 signal 18 36 (half strength mode) D n_GVDD = 1.8 V 1, 5, 9 Local Bus signals 45 25 OVDD = 3.3 V 2, 6 eTSEC/10/100 signals 45 T/LVDD = 3.3 V 6 30 T/LVDD = 2.5 V 6 DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, JTAG and Miscellaneous I/O voltage 45 OVDD = 3.3 V 6 I2C 150 OVDD = 3.3 V 7 SRIO, PCI Express 100 SVDD = 1.1/1.05 V 3, 8 Notes: 1. See the DDR Control Driver registers in the MPC8641D reference manual for more information. 2. Only the following local bus signals have programmable drive strengths: LALE, LAD[0:31], LDP[0:3], LA[27:31], LCKE, LCS[1:2], LWE[0:3], LGPL1, LGPL2, LGPL3, LGPL4, LGPL5, LCLK[0:2]. The other local bus signals have a fixed drive strength of 45 ohms. See the POR Impedance Control register in the MPC8641D reference manual for more information about local bus signals and their drive strength programmability. 3. See Section 17, “Signal Listings” for details on resistor requirements for the calibration of SD n_IMP_CAL_TX and SD n_IMP_CAL_RX transmit and receive signals. 4. Stub Series Terminated Logic (SSTL-25) type pins. 5. Stub Series Terminated Logic (SSTL-18) type pins. 6. Low Voltage Transistor-Transistor Logic (LVTTL) type pins. 7. Open Drain type pins. 8. Low Voltage Differential Signaling (LVDS) type pins. 9. The drive strength of the DDR interface in half strength mode is at Tj = 105C and at Dn_GVDD (min). |
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