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CY7C68000A Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C68000A
Description  MoBL-USB??TX2 USB 2.0 UTMI Transceiver
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C68000A Datasheet(HTML) 8 Page - Cypress Semiconductor

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CY7C68000A
Document #: 38-08052 Rev. *G
Page 8 of 15
21
A4
RXValid
Output
Receive Data Valid This signal indicates that the DataOut bus has valid
data. The Receive Data Holding Register is full and ready to be unloaded.
The SIE is expected to latch the DataOut bus on the clock edge.
22
B7
RXActive
Output
Receive Active This signal indicates that the receive state machine has
detected SYNC and is active.
RXActive is negated after a bit stuff error or an EOP is detected.
23
A6
RXError
Output
Receive Error
0 Indicates no error.
1 Indicates that a receive error has been detected.
56
A7
ValidH
I/O
ValidH This signal indicates that the high-order eight bits of a 16-bit data
word presented on the Data bus are valid. When DataBus16_8 = 1 and
TXValid = 0, ValidH is an output, indicating that the high-order receive
data byte on the Data bus is valid. When DataBus16_8 = 1 and TXValid
= 1, ValidH is an input and indicates that the high-order transmit data byte,
presented on the Data bus by the transceiver, is valid. When
DataBus16_8 = 0, ValidH is undefined. The status of the receive
low-order data byte is determined by RXValid and are present on D0–D7.
51
A2
DataBus16_8
Input
Data Bus 16_8 This signal selects between 8- and 16-bit data transfers.
1–16-bit data path operation enabled. CLK = 30 MHz.
0–8-bit data path operation enabled. When Uni_Bidi = 0, D[8:15] are un-
defined. When Uni_Bidi =1, D[0:7] are valid on TxValid and D[8:15] are
valid on RxValid. CLK = 60 MHz
Note: DataBus16_8 is static after Power-on Reset (POR) and is only
sampled at the end of Reset.
6
H3
XTALIN
Input
N/A
Crystal Input Connect this signal to a 24 MHz parallel-resonant, funda-
mental mode crystal and 30 pF capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square wave
derived from another clock source.
5
H2
XTALOUT
Output
N/A
Crystal Output Connect this signal to a 24 MHz parallel-resonant, funda-
mental mode crystal and 30 pF (nominal) capacitor to GND. If an external
clock is used to drive XTALIN, leave this pin open.
52
A3
Uni_Bidi
Input
Driving this pin HIGH enables the unidirectional mode when the 8-bit
interface is selected. Uni_Bidi is static after power-on reset (POR).
55
C6
VCC
Power
VCC. Connect to 3.3V power source.
17
C7
VCC
Power
N/A
VCC. Connect to 3.3V power source.
28
D7
VCC
Power
N/A
VCC. Connect to 3.3V power source.
32
E7
VCC
Power
N/A
VCC. Connect to 3.3V power source.
45
E8
VCC
Power
N/A
VCC. Connect to 3.3V power source.
53
C4
GND
Ground
N/A
Ground.
16
C5
GND
Ground
N/A
Ground.
20
C3
GND
Ground
N/A
Ground.
30
D1
GND
Ground
N/A
Ground.
42
D2
GND
Ground
N/A
Ground.
47
G6
Reserved
INPUT
Connect pin to Ground.
40
F7
Reserved
INPUT
Connect pin to Ground.
35
F2
Reserved
INPUT
Connect pin to Ground.
25
C8
Reserved
INPUT
Connect pin to Ground.
Table 1. Pin Descriptions (continued)
QFN VFBGA
Name
Type
Default
Description[1] (continued)
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