9 / 37 page
CY8C21123, CY8C21223, CY8C21323
Document Number: 38-12022 Rev. *H
Page 9 of 37
Table 5. Pin Definitions - 16-Pin QFNa
Pin
No.
Type
Pin
Name
Description
Figure 7. CY8C21223 16-Pin PSoC Device
Digital
Analog
1
IO
I
P0[3]
Analog Column Mux Input
2
IO
I
P0[1]
Analog Column Mux Input
3
IO
P0[7]
I2C Serial Clock (SCL)
4
IO
P1[5]
I2C Serial Data (SDA)
5
IO
P1[3]
6
IO
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK*
7
Power
Vss
Ground Connection
8
IO
P1[0]
I2C Serial Data (SDA), ISSP-SDATA*
9
IO
P1[4]
Optional External Clock Input (EXCLK)
10
Input
XRES
Active High External Reset with Internal
Pull Down
11
IO
I
P0[0]
Analog Column Mux Input
12
IO
I
P0[4]
Analog Column Mux Input
13
IO
I
P0[6]
Analog Column Mux Input
14
Power
Vdd
Supply Voltage
15
IO
I
P0[7]
Analog Column Mux Input
16
IO
I
P0[5]
Analog Column Mux Input
LEGEND A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array
Technical Reference Manual for details.
a. The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not
connected to ground, it must be electrically floated and not connected to any other signal.
QFN
(Top View)
1
2
3
4
12
11
10
9
P0[4], AI
P0[0], AI
XRES
P1[4], EXTCLK
P0[3], AI
P0[1], AI
I2C SCL, P1[7]
I2C SDA, P1[5]
[+] Feedback
[+] Feedback