CY8CTMA120
Document Number: 001-46901 Rev. *C
Page 3 of 35
The Analog System
The Analog System is composed of 6 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Implementation of touchscreen application
allows additional analog resources to be used, depending on the
touchscreen design. Analog peripherals are very flexible and are
customized to support specific application requirements. Some
of the more common PSoC analog functions (most available as
user modules) are listed below.
■ Analog-to-digital converters (up to 2, with 6 to 14-bit resolu-
tion, selectable as Incremental, Delta Sigma, and SAR)
■ Filters (2 and 4 pole band-pass, low-pass, and notch)
■ Amplifiers (up to 2, with selectable gain to 48x)
■ Instrumentation amplifiers (1 with selectable gain to 93x)
■ Comparators (up to 2, with 16 selectable thresholds)
■ DACs (up to 2, with 6- to 9-bit resolution)
■ Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■ High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
■ 1.3V reference (as a System Resource)
■ Modulators
■ Correlators
■ Peak Detectors
■ Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in Figure 2.
The Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin in ports 0-5.
Pins are connected to the bus individually or in any combination.
The bus also connects to the analog system for capacitive
sensing with the TrueTouch block comparator. It is split into two
sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch control logic enables selected pins to switch dynamically
under hardware control. This enables capacitive measurement
for the touchscreen applications. Other multiplexer applications
include:
■ Chip-wide mux that allows analog input from up to 48 IO
pins.
■ Electrical connection between any IO pin combinations.
Figure 2. Analog System Block Diagram
Additional System Resources
System Resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief state-
ments describing the merits of each resource follow.
■ Full-Speed USB (12 Mbps) with five configurable endpoints
and 256 bytes of RAM. No external components required
except two series resistors. Wider than commercial tempera-
ture USB operation (-10°C to +85°C).
■ Digital clock dividers provide three customizable clock fre-
quencies for use in applications. The clocks are routed to
both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
■ Two multiply accumulates (MACs) provide fast 8-bit multipli-
ers with 32-bit accumulate, to assist in both general math
and digital filters.
■ Decimator provides a custom hardware filter for digital signal
processing applications, including creation of Delta Sigma
ADCs.
ACB00
ACB01
Block
Array
Array Input
Configuration
AC I1[1:0]
ASD20
AC I0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Re fe re nce
Ge ne rators
AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Inte rface to
Digital Syste m
M 8C Inte rface (Addre ss Bus, Data Bus, Etc.)
AnalogReference
All IO
(Exce pt Port 7)
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