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CY8CTST110
Document Number: 001-46931 Rev. *B
Page 9 of 32
Table 3. Pin Definitions - CY8CTST110 32-Pin (QFN)
Pin
No.
Type
Name
Description
Digital
Analog
1
IO
I, M
P0[1]
Analog column mux input, integrating input.
2
IO
M
P2[7]
3
IO
M
P2[5]
4
IO
M
P2[3]
5
IO
M
P2[1]
6
IO
M
P3[3]
7
IO
M
P3[1]
8
IO
M
P1[7]
I2C Serial Clock (SCL).
9
IO
M
P1[5]
I2C Serial Data (SDA).
10
IO
M
P1[3]
11
IO
M
P1[1]
I2C Serial Clock (SCL), ISSP-SCLK[3].
12
Power
Vss
Ground. Connect to circuit ground.
13
IO
M
P1[0]
I2C Serial Data (SDA), ISSP-SDATA[3].
14
IO
M
P1[2]
15
IO
M
P1[4]
Optional External Clock Input (EXTCLK).
16
IO
M
P1[6]
17
Input
XRES
Active high external reset with internal pull down.
18
IO
M
P3[0]
19
IO
M
P3[2]
20
IO
M
P2[0]
21
IO
M
P2[2]
22
IO
M
P2[4]
23
IO
M
P2[6]
24
IO
I, M
P0[0]
Analog column mux input.
25
IO
I, M
P0[2]
Analog column mux input.
26
IO
I, M
P0[4]
Analog column mux input.
27
IO
I, M
P0[6]
Analog column mux input.
28
Power
Vdd
Supply voltage. Bypass to ground with 0.1 uF capacitor.
29
IO
I, M
P0[7]
Analog column mux input.
30
IO
I, M
P0[5]
Analog column mux input.
31
IO
I, M
P0[3]
Analog column mux input, integrating input.
32
Power
Vss
Ground. Connect to circuit ground.
EP
Power
Vss
Exposed pad is internally connected to ground. Connect to circuit ground.
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
3. These are the ISSP pins, which are not High Z at POR (Power On Reset)
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