CY8CTST120
Document Number: 001-46932 Rev. *B
Page 2 of 32
TrueTouch Functional Overview
The TrueTouch family provides the fastest and most efficient way
to develop and tune a capacitive touchscreen application. A
TrueTouch device includes the configurable TrueTouch block,
configurable analog and digital logic, programmable inter-
connect, and an 8-bit CPU to run custom firmware. This archi-
tecture enables the user to create flexible, customized
single-touch touchscreen configurations to match the require-
ments of each individual touchscreen application. Various
configurations of Flash program memory, SRAM data memory,
and configurable IO are included in a range of convenient
pinouts.
The TrueTouch architecture is comprised of four main areas: the
Core, Digital System, the TrueTouch Analog System, and
System Resources including a full speed USB port. Configurable
global busing allows all the device resources to be combined into
a complete custom touchscreen system. The CY8CTST120
device can have up to seven IO ports that connect to the global
digital and analog interconnects, providing access to four digital
blocks and six analog blocks. Implementation of touchscreen
applications allows additional digital and analog resources to be
used depending on the touchscreen design. The CY8CTST120
is offered in a 56-pin QFN package with up to 48 general purpose
IO (GPIO), and support of up to 44 X/Y sensors.
When designing touchscreen applications, refer to the UM data
sheet for performance requirements to meet and detailed design
process explanation.
The TrueTouch Core
The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture micropro-
cessor. The CPU uses an interrupt controller with up to 20
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The TrueTouch device incorporates flexible internal clock gener-
ators, including a 24 MHz IMO (internal main oscillator) accurate
to 8% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
sleep timer and WDT. The clocks, together with programmable
clock dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the TrueTouch
device. In USB systems, the IMO self-tunes to ± 0.25% accuracy
for USB communication.
The GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external inter-
facing. Every pin is capable of generating a system interrupt on
high level, low level, and change from last read.
The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that is used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Figure 1. Digital System Block Diagram
Digital peripheral configurations include those listed below.
■ Full-Speed USB (12 Mbps)
■ PWMs (8 to 32 bit)
■ PWMs with dead band (8 to 24 bit)
■ Counters (8 to 32 bit)
■ Timers (8 to 32 bit)
■ UART 8 bit with selectable parity
■ SPI master and slave
■ I2C slave and multi-master
■ Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
characteristics are shown in Table 1 on page 4.
DIGITAL SYSTEM
To System Bus
DigitalClocks
FromCore
Digital PSoC Block Array
ToAnalog
System
8
8
8
8
Row 0
DBB00
DBB01
DCB02
DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
GlobalDigital
Interconnect
Port 1
Port 0
Port 3
Port 2
Port 5
Port 4
Port 7
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