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CY25100
Document #: 38-07499 Rev. *F
Page 8 of 13
Informational Graphs (continued)[6]
Duty Cycle vs. REFCLK
( C LOA D =1 5 pF)
40
42
44
46
48
50
52
54
56
58
60
0
50
100
150
200
REFCLK (MHz)
IDD vs . SSCLK
T e m p e r atu r e =25C, V DD=3.3V , C L OA D=15p F, SS o ff,
Re fclk = 30M Hz
0
5
10
15
20
25
30
0
50
100
150
200
SSC L K (M Hz )
Measured Spread% vs. VDD over Tem perature
(Target Spread = 0.5%, Fout=100MHz, CLOAD=15pF)
0.40%
0.45%
0.50%
0.55%
0.60%
2.7
3
3.3
3.6
3.9
VDD (V)
-40C
25C
85C
Measured Spread% vs. VDD over
Tem perature
(Target Spread = 5.0%, Fout=100MHz, CLOAD=15pF)
4.00%
4.50%
5.00%
5.50%
6.00%
2.7
3
3.3
3.6
3.9
VDD (V)
-40C
25C
85C
SSCLK Attenuation vs. VDD over Tem perature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=0.5%, CLOAD=15pF)
-10
-8
-6
-4
-2
0
2.7
3
3.3
3.6
3.9
VDD (V)
-40C
25C
85C
SSCLK Attenuation vs. VDD over Tem perature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=5.0%, C
LOAD=15pF)
-20
-18
-16
-14
-12
-10
2.7
3
3.3
3.6
3.9
VDD (V)
-40C
25C
85C
Note
6. The Informational Graphs are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on pages
4 and 5 for device specifications.
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