CY22392
Document #: 38-07013 Rev. *E
Page 4 of 9
associated logic, while suspending an output simply forces a
three-state condition.
Improving Jitter
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment, causing
excess jitter. If one PLL is driving more than one output, the
negative phase of the PLL can be selected for one of the outputs
(CLKA–CLKD). This prevents the output edges from aligning,
allowing superior jitter performance.
Power Supply Sequencing
For parts with multiple VDD pins, there are no power supply
sequencing requirements. The part is not be fully operational
until all VDD pins have been brought up to the voltages specified
in the “Operating Conditions” table.
All grounds must be connected to the same ground plane.
CyClocksRT™ Software
CyClocksRT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied.
CyClocksRT also has a power estimation feature that allows you
to see the power consumption of your specific configuration. You
can download a copy of CyClocksRT for free on Cypress’s web
site at www.cypress.com.
Junction Temperature Limitations
It is possible to program the CY22392 such that the maximum
Junction Temperature rating is exceeded. The package
θJA is
115 C/W. Use the CyClocksRT power estimation feature to verify
that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum ratings.
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply Voltage................................................–0.5V to +7.0V
DC Input Voltage ........................... –0.5V to + (AVDD + 0.5V)
Storage Temperature ................................. –65
°C to +125°C
Junction Temperature .................................................. 125
°C
Data Retention at Tj = 125
°C .................................>10 years
Maximum Programming Cycles........................................100
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................................
2000V
Latch up (per JEDEC 17) .................................... > ±200 mA
Operating Conditions[1]
Parameter
Description
Min
Typ.
Max
Unit
VDD/AVDD
Supply Voltage
3.135
3.3
3.465
V
TA
Commercial Operating Temperature, Ambient
0
–
+70
°C
Industrial Operating Temperature, Ambient
–40
–
+85
°C
CLOAD_OUT
Max. Load Capacitance
–
–
15
pF
fREF
External Reference Crystal
8
–
30
MHz
External Reference Clock[2], Commercial
1
–
166
MHz
External Reference Clock[2], Industrial
1
–
150
MHz
tPU
Power up time for all VDD's to reach minimum specified voltage
(power ramps must be monotonic)
0.05
–
500
ms
Notes
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at VDD/2.
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
