CY22381
Document #: 38-07012 Rev. *E
Page 3 of 9
Output Configuration
Under normal operation there are four internal frequency
sources that may be routed through a programmable crosspoint
switch to any of the three outputs through programmable
seven-bit output dividers. The four sources are: reference, PLL1,
PLL2, and PLL3. The following is a description of each output.
CLKA’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
CLKB’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one of two programmable
registers controlled by FS.
CLKC’s output originates from the crosspoint switch and goes
through a programmable seven-bit post divider. The seven-bit
post divider derives its value from one programmable register.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15pF. While driving
multiple loads is possible with the proper termination, it is
generally not recommended.
Power-Saving Features
When configured as OE, the general-purpose input three-states
all outputs when pulled LOW. When configured as Shutdown, a
LOW on this pin three-states all outputs and shuts off the PLLs,
counters, the reference oscillator, and all other active
components. The resulting current on the VDD pins is less than
5
μA (typical). After leaving shutdown mode, the PLLs will have
to relock.
When configured as SUSPEND, the general-purpose input can
be configured to shut down a customizable set of outputs and/or
PLLs, when LOW. All PLLs and any of the outputs can be shut
off in nearly any combination. The only limitation is that if a PLL
is shut off, all outputs derived from it must also be shut off.
Suspending a PLL shuts off all associated logic, while
suspending an output forces a three-state condition.
Improving Jitter
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment and
causing excess jitter. If one PLL is driving more than one output,
the negative phase of the PLL can be selected for one of the
outputs. This prevents the output edges from aligning, allowing
superior jitter performance.
CyClocks RT Software
CyClocks RT is our second-generation application that allows
users to configure this device. The easy-to-use interface offers
complete control of the many features of this family including
input frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied. You
can download a free copy of CyClocks RT on Cypress’s web site
at http://www.cypress.com.
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