CY2305
CY2309
Document #: 38-07140 Rev. *I
Page 6 of 15
Electrical Characteristics for CY2305SI-XX and CY2309SI-XX Industrial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
VIL
Input LOW Voltage[5]
–0.8
V
VIH
Input HIGH Voltage[5]
2.0
–
V
IIL
Input LOW Current
VIN = 0V
–
50.0
μA
IIH
Input HIGH Current
VIN = VDD
–100.0
μA
VOL
Output LOW Voltage[6]
IOL = 8 mA (–1)
IOH =12 mA (–1H)
–0.4
V
VOH
Output HIGH Voltage[6]
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
–
V
IDD (PD mode) Power down Supply Current
REF = 0 MHz
–
25.0
μA
IDD
Supply Current
Unloaded outputs at 66.67
MHz, SEL inputs at VDD
–
35.0
mA
Switching Characteristics for CY2305SI-1 and CY2309SI-1 Industrial Temperature Devices
Parameter[7]
Name
Test Conditions
Min
Typ.
Max
Unit
t1
Output Frequency
30 pF load
10 pF load
10
10
–100
133.33
MHz
MHz
tDC
Duty Cycle[6] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
40.0
50.0
60.0
%
t3
Rise Time[6]
Measured between 0.8V and 2.0V
–
–
2.50
ns
t4
Fall Time[6]
Measured between 0.8V and 2.0V
–
–
2.50
ns
t5
Output to Output Skew[6]
All outputs equally loaded
–
85
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2
–
–
±350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in PLL
Bypass Mode, CY2309 device only.
15
8.7
ns
t7
Device to Device Skew[6] Measured at VDD/2 on the CLKOUT pins
of devices
––
700
ps
tJ
Cycle to Cycle Jitter[6]
Measured at 66.67 MHz, loaded outputs
–
70
200
ps
tLOCK
PLL Lock Time[6]
Stable power supply, valid clock
presented on REF pin
––
1.0
ms
Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices
Parameter[7]
Name
Description
Min
Typ.
Max
Unit
t1
Output Frequency
30 pF load
10 pF load
10
10
–100
133.33
MHz
MHz
tDC
Duty Cycle[6] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
40.0
50.0
60.0
%
t3
Rise Time[6]
Measured between 0.8V and 2.0V
–
–
1.50
ns
t4
Fall Time[6]
Measured between 0.8V and 2.0V
–
–
1.50
ns
t5
Output to Output Skew[6]
All outputs equally loaded
–
85
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2
–
–
±350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in PLL
Bypass Mode, CY2309 device only.
15
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT pins
of devices
––
700
ps
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