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CY25100
Document #: 38-07499 Rev. *F
Page 6 of 13
Application Circuit
Figure 2. Application Circuit Diagram[3, 4, 5]
Switching Waveforms
0. 1u F
VD D
1
3
2
4
5
6
7
8
VD D
XO U T
X I N/ C L KI N
PD # / O E
VSS
RE F C L K
SSC L K
SSO N #
Po w e r
C Y 2 510 0
t1A
t1B
OUTPUT
Figure 3. Duty Cycle Timing (DC = t1A/t1B)
OUTPUT
Tr
VDD
0V
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 4. Output Rise/Fall Time (SSCLK and REFCLK)
CLKOUT
VDD
tPU
tSTP
VIL
VIH
POWER
DOWN
0V
(Asynchronous)
High Impedance
Figure 5. Power Down and Power Up Timing
Notes
3. Because the load capacitors (CXIN and CXOUT) are provided by the CY25100, no external capacitors are needed on the XIN and XOUT pins to match the crystal load
capacitor (CL). Only a single 0.1-μF bypass capacitor is required on the VDD pin.
4. If an external clock is used, apply the clock to XIN (pin 3) and leave XOUT (pin 2) floating (unconnected).
5. If SSON# (pin 8) is LOW (VSS), the frequency modulation is on at SSCLK pin (pin 7).
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