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DRV8402DKD Datasheet(PDF) 9 Page - Texas Instruments |
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DRV8402DKD Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 18 page  THEORY OF OPERATION POWER SUPPLIES SYSTEM POWER-UP/POWER-DOWN Powering Up Powering Down DRV8402 www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008 compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a ceramic capacitor placed as close as possible to each supply To help with system design, the DRV8402 needs only pin. It is recommended to follow the PCB layout of a 12 V supply in addition to power-stage supply. An the DRV8402 in EVM board. internal voltage regulator provides suitable voltage The 12 V supply should be from a low-noise, levels for the digital and low-voltage analog circuitry. low-output-impedance voltage regulator. Likewise, the Additionally, all circuitry requiring a floating voltage 50 V power-stage supply is assumed to have low supply, for example, the high-side gate drive, is output impedance and low noise. The power-supply accommodated by built-in bootstrap circuitry requiring sequence is not critical as facilitated by the internal only a few external capacitors. power-on-reset circuit. Moreover, the DRV8402 is To provide electrical characteristics, the PWM signal fully protected against erroneous power-stage turn-on path including gate drive and output stage is due to parasitic gate charging. Thus, voltage-supply designed as identical, independent half-bridges. For ramp rates (dv/dt) are non-critical within the specified this reason, each half-bridge has separate gate drive range (see the Recommended Operating Conditions supply (GVDD_X), bootstrap pins (BST_X), and section of this data sheet). power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same SEQUENCE 12-V source, it is recommended that a 1 – 10 Ω resistor is used to separate the GVDD_X pins from VDD on the printed-circuit board (PCB). Special attention should be paid to placing all decoupling The DRV8402 does not require a power-up capacitors as close to their associated pins as sequence. The outputs of the H-bridges remain in a possible. In general, inductance between the power highimpedance state until the gate-drive supply supply pins and decoupling capacitors must be voltage (GVDD_X) and VDD voltage are above the avoided. undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data For a properly functioning bootstrap circuit, a small sheet). Although not specifically required, holding ceramic capacitor must be connected from each RESET_AB and RESET_CD in a low state while bootstrap pin (BST_X) to the power-stage output pin powering up the device is recommended. This allows (OUT_X). When the power-stage output is low, the an internal circuit to charge the external bootstrap bootstrap capacitor is charged through an internal capacitors by enabling a weak pulldown of the diode connected between the gate-drive half-bridge output (except in half-bridge modes). power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply The DRV8402 does not require a power-down for the high-side gate driver. In an application with sequence. The device remains fully operational as PWM switching frequencies in the range from 25 kHz long as the gate-drive supply (GVDD_X) voltage and to 500 kHz, the use of 47 nF ceramic capacitors, size VDD voltage are above the UVP voltage threshold 0603 or 0805, is recommended for the bootstrap (see the Electrical Characteristics section of this data supply. These 47 nF capacitors ensure sufficient sheet). Although not specifically required, it is a good energy storage, even during minimal PWM duty practice to hold RESET_AB and RESET_CD low cycles, to keep the high-side power stage FET fully during power down to prevent any unknown state turned on during the remaining part of the PWM during this transition. cycle. In an application running at a switching frequency lower than 25 kHz, the bootstrap capacitor might need to be increased in value. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): DRV8402 |
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