CY22393, CY22394, CY22395
Document #: 38-07186 Rev. *D
Page 4 of 19
1
2
3
4
5
6
7
8
9
10
CLKC
VDD
AGND
XTALIN
XTALOUT
XBUF
CLKD
CLKE
SHUTDOWN/OE
S2/SUSPEND
AVDD
SCLK (S1)
SDAT (S0)
GND
CLKA
CLKB
16-pin TSSOP
11
12
13
14
15
16
CY22393
1
2
3
4
5
6
7
8
9
10
CLKC
VDD
AGND
XTALIN
XTALOUT
XBUF
P–CLK
P+ CLK
SHUTDOWN/OE
S2/SUSPEND
AVDD
SCLK (S1)
SDAT (S0)
GND
CLKA
CLKB
16-pin TSSOP
11
12
13
14
15
16
CY22394
1
2
3
4
5
6
7
8
9
10
CLKC
VDD
AGND
XTALIN
XTALOUT
LCLKD
LCLKE
SHUTDOWN/OE
S2/SUSPEND
AVDD
SCLK (S1)
SDAT (S0)
GND/LGND
LCLKA
LCLKB
16-pin TSSOP
11
12
13
14
15
16
CY22395
LVDD
Pinouts
Figure 1. Pin diagram - 16-Pin TSSOP CY22393/CY22394/CY22394
Pin Definitions
Name
Pin Number
CY22393
Pin Number
CY22394
Pin Number
CY22395
Description
CLKC
1
1
1
Configurable clock output C
VDD
2
2
2
Power supply
AGND
3
3
3
Analog Ground
XTALIN
4
4
4
Reference crystal input or external reference clock input
XTALOUT
5
5
5
Reference crystal feedback
XBUF
6
6
N/A
Buffered reference clock output
LVDD
N/A
N/A
6
Low voltage clock output power supply
CLKD or LCLKD
7
N/A
7
Configurable clock output D; LCLKD referenced to LVDD
P– CLK
N/A
7
N/A
LV PECL output[1]
CLKE or LCLKE
8
N/A
8
Configurable clock output E; LCLKE referenced to LVDD
P+ CLK
N/A
8
N/A
LV PECL output[1]
CLKB or LCLKB
9
9
9
Configurable clock output B; LCLKB referenced to LVDD
CLKA or LCLKA
10
10
10
Configurable clock output A; LCLKA referenced to LVDD
GND/LGND
11
11
11
Ground
SDAT (S0)
12
12
12
Serial Port Data. S0 value latched during start up
SCLK (S1)
13
13
13
Serial Port Clock. S1 value latched during start up
AVDD
14
14
14
Analog Power Supply
S2/
SUSPEND
15
15
15
General purpose input for frequency control; bit 2. Optionally,
Suspend mode control input
SHUTDOWN/
OE
16
16
16
Places outputs in tri-state condition and shuts down chip when
LOW. Optionally, only places outputs in tri-state condition and
does not shut down chip when LOW
Note
1. LVPECL outputs require an external termination network.
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