Electronic Components Datasheet Search |
|
BUK3F00-50WDFY Datasheet(PDF) 9 Page - NXP Semiconductors |
|
BUK3F00-50WDFY Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 52 page BUK3F00-50WDXX_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 4 September 2008 9 of 52 NXP Semiconductors BUK3F00-50WDxx Controller for TrenchPLUS FETs 9.2 Charge pump The controller has an internal charge pump circuit to supply the gate voltage required to operate the high-side FET switches. The charge pump uses an internal oscillator and internal switches with external pump and storage capacitors. 9.2.1 Charge pump supply: pins VBAT(CP) and GND(CP) Pins VBAT(CP) and GND(CP) supply power to the internal charge pump. This is derived from the VBAT supply either via an internal resistor between pins VBAT and VBAT(CP) or by linking these pins externally. Pin GND(CP) should be connected to pin GND; the grounds are not internally connected to ensure any charge pump noise does not affect the measurement circuit. The connections should be decoupled close to the device. The charge pump supply circuit has an internal overvoltage clamp to protect the BUK3F00-50WDxx from overvoltage transients and is also protected against ESD. If connected to a reverse polarity battery voltage, the charge pump supply is protected by the internal resistor connection to VBAT. 9.2.2 Charge pump boost mode To ensure fast start-up, the charge pump has a boost mode that operates for a set time. This mode is triggered at power-on reset and when the charge pump voltage falls below the charge pump fault threshold or the battery voltage stays below the undervoltage threshold. If the charge pump voltage is below the fault threshold after the charge pump boost is completed, then no further boost is possible until the charge pump fault is cleared. 9.3 Control logic The control logic is responsible for switching the individual FET channels on and off, depending on user settings and the implementation of protection methods. It contains registers used for storing the user settings for channel configurations, current reference and measurement, diagnostic and watchdog modes. Communication with a controller is via the SPI-bus. The digital block is designed to support 8 channels; unused channels should be programmed off at all times. 9.3.1 Digital control The device is enabled by pin EN. When pin EN is LOW, the device is in Standby mode and all FETs are held off by an active switch with a standby resistance between pins GATE and KELVIN. When pin EN is HIGH, the device is enabled for normal operation. Pin EN can be used as the reset signal by a controller for the control logic. When pin EN is reset to HIGH, the device goes through a power-on reset, registers are loaded with their default values and channels are switched on or off according to the mapping for the individual device type. Digital control consists of a number of registers that control the functions. The default value is loaded during power-on reset and, if the WRITE_PROTECT option is enabled, for defined registers, when the SPI watchdog times out. For some registers the default setting can be programmed by metal mask options. |
Similar Part No. - BUK3F00-50WDFY |
|
Similar Description - BUK3F00-50WDFY |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |