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CBT3126DB Datasheet(PDF) 4 Page - NXP Semiconductors

Part # CBT3126DB
Description  Quad FET bus switch
Download  13 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

CBT3126DB Datasheet(HTML) 4 Page - NXP Semiconductors

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CBT3126_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 9 December 2008
4 of 13
NXP Semiconductors
CBT3126
Quad FET bus switch
9.
Static characteristics
[1]
All typical values are measured at VCC =5V; Tamb =25 °C.
[2]
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3]
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is
determined by the lowest voltage of the two (A or B) terminals.
10. Dynamic characteristics
[1]
This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON
resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance).
[2]
tPLH and tPHL are the same as tpd;
tPZL and tPZH are the same as ten;
tPLZ and tPHZ are the same as tdis.
Table 6.
Static characteristics
Tamb = −40 °C to +85 °C.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VIK
input clamping voltage
VCC = 4.5 V; II = −18 mA
-
-
−1.2
V
Vpass
pass voltage
VI =VCC = 5.0 V; IO = −100 µA
-
3.8
-
V
II
input leakage current
VCC = 5.5 V; VI = GND or 5.5 V
-
-
±1
µA
ICC
supply current
VCC = 5.5 V; IO = 0 mA;
VI =VCC or GND
--3
µA
∆ICC
additional supply current
control pins; per input;
VCC = 5.5 V; one input at 3.4 V,
other inputs at VCC or GND
[2] -
-
2.5
mA
CI
input capacitance
control pins; VI = 3 V or 0 V
-
1.7
-
pF
Cio(off)
off-state input/output capacitance
VO = 3 V or 0 V; OE = VCC
-
3.4
-
pF
RON
ON resistance
VCC = 4.0 V
[3]
VI = 2.4 V; II = 15 mA
-
16
22
VCC = 4.5 V
VI =0V; II =64mA
-
5
7
VI =0V; II =30mA
-
5
7
VI = 2.4 V; II = 15 mA
-
10
15
Table 7.
Dynamic characteristics
Tamb = −40 °C to +85 °C; VCC = 4.5 V to 5.5 V; for test circuit see Figure 8.
Symbol
Parameter
Conditions
Min
Max
Unit
tpd
propagation delay
nA to nB or nB to nA; see Figure 6
[1][2] -
0.25
ns
ten
enable time
OE to nA or nB; see Figure 7
[2] 1.6
4.5
ns
tdis
disable time
OE to nA or nB; see Figure 7
[2] 1.0
5.4
ns


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