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HEF4027BP Datasheet(PDF) 3 Page - NXP Semiconductors |
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HEF4027BP Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 / 13 page  HEF4027B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 10 November 2008 3 of 13 NXP Semiconductors HEF4027B Dual JK flip-flop 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description Fig 3. Pin configuration HEF4027B 2Q VDD 2Q 1Q 2CP 1Q 2CD 1CP 2K 1CD 2J 1K 2SD 1J VSS 1SD 001aae594 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 Table 2. Pin description Symbol Pin Description VSS 8 ground supply voltage 1SD, 2SD 9, 7 asynchronous set-direct input (active HIGH) 1J, 2J 10, 6 synchronous input 1K, 2K 11, 5 synchronous input 1CD, 2CD 12, 4 asynchronous clear-direct input (active HIGH) 1CP, 2CP 13, 3 clock input (LOW-to-HIGH edge-triggered) 1Q, 2Q 14, 2 complement output 1Q, 2Q 15, 1 true output VDD 16 supply voltage Table 3. Function table[1] Inputs Outputs nSD nCD nCP nJ nK nQ nQ HL X X X HL LH X X X LH HHX X X HH |
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