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HEF4049BP Datasheet(PDF) 3 Page - NXP Semiconductors |
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HEF4049BP Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 11 page HEF4049B_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 3 of 11 NXP Semiconductors HEF4049B Hex inverting buffers 7. Functional description 8. Limiting values [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 9. Recommended operating conditions 1A to 6A 3, 5, 7, 9, 11, 14 input VSS 8 ground supply voltage n.c. 13, 16 not connected Table 2. Pin description …continued Symbol Pin Description Table 3. Guaranteed fan-out Driven element Guaranteed fan-out Standard TTL 2 74 LS 9 74 L 16 Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD supply voltage −0.5 +18 V VI input voltage any input −0.5 VDD + 0.5 V II/O input/output current - ±10 mA Tstg storage temperature −65 +150 °C Tamb ambient temperature −40 +85 °C Ptot total power dissipation Tamb −40 °C to +85 °C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW P power dissipation per output - 100 mW Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air −40 - +85 °C ∆t/∆V input transition rise and fall rate VDD = 5 V - - 3.75 ns/V VDD = 10 V - - 0.5 ns/V VDD = 15 V - - 0.08 ns/V |
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