PDI1284P11_3

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 — 25 August 2008

10 of 16

NXP Semiconductors

PDI1284P11

3.3 V parallel interface transceiver/buffer

Test circuit is shown in Figure 7.

Measurement points are given in Table 9.

Fig 6.

Enable and disable times

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outputs

disabled

outputs

enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

HD to B

DIR to B

DIR to A

GND

GND

Test conditions are given in Table 9.

Fig 7.

Test circuit for measuring enable and disable times

mna616

DUT

CL

RT

RL

RL

G

Table 9.

Test data for test circuit measuring enable disable times Bn to An

Parameter

Input

Output

DIR to Bn, An;

OEA to An

< 2.7 V

1.5 V

1.5 V

GND

2.7 V to 3.6 V

2.7 V

1.5 V

1.5 V

GND

HD to Yn or Bn;

HD to PHLO

< 2.7 V

1.5 V

1.5 V

-

open

-

2.7 V to 3.6 V

2.7 V

1.5 V

1.5 V

-

open

-