 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TJA1080A Datasheet(PDF) 7 Page - NXP Semiconductors |
|
||||||||||||||||||||||||||||||
TJA1080A Datasheet(HTML) 7 Page - NXP Semiconductors |
|
|
7 / 50 page  TJA1080A_2 © NXP B.V. 2008. All rights reserved. Preliminary data sheet Rev. 02 — 26 August 2008 7 of 50 NXP Semiconductors TJA1080A FlexRay transceiver 6.1.3 Bus activity and idle detection The following mechanisms for activity and idle detection are valid for node and star configurations in normal power modes: • If the absolute differential voltage on the bus lines is higher than |V i(dif)det(act)| for tdet(act)(bus), then activity is detected on the bus lines and pin RXEN is switched to LOW which results in pin RXD being released: – If, after bus activity detection, the differential voltage on the bus lines is higher than VIH(dif), pin RXD will go HIGH – If, after bus activity detection, the differential voltage on the bus lines is lower than VIL(dif), pin RXD will go LOW • If the absolute differential voltage on the bus lines is lower than |V i(dif)det(act)| for tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH. This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH) Additionally, in star configuration, activity and idle can be detected (see Figure 6 for state transitions due to activity/idle detection in star configuration): • If pin TXEN is LOW for longer than tdet(act)(TXEN), activity is detected on pin TXEN • If pin TXEN is HIGH for longer than tdet(idle)(TXEN), idle is detected on pin TXEN • If pin TRXD0 or TRXD1 is LOW for longer than tdet(act)(TRXD), activity is detected on pins TRXD0 and TRXD1 • If pin TRXD0 and TRXD1 is HIGH for longer than tdet(idle)(TRXD), idle is detected on pins TRXD0 and TRXD1 6.2 Operating modes in node configuration The TJA1080A provides two control pins STBN and EN in order to select one of the modes of operation in node configuration. See Table 3 for a detailed description of the pin signalling in node configuration, and Figure 3 for the timing diagram. All modes are directly controlled via pins EN and STBN unless an undervoltage situation is present. If VIO and (VBUF or VBAT) are within their operating range, pin ERRN indicates the status of the error flag. [1] Pin ERRN provides a serial interface for retrieving diagnostic information. [2] Valid if VIO and (VBUF or VBAT) are present. [3] If wake flag is not set. Table 3. Pin signalling in node configuration Mode STBN EN ERRN[1] RXEN RXD Transmitter INH1 INH2 LOW HIGH LOW HIGH LOW HIGH Normal HIGH HIGH error flag set error flag reset bus activity bus idle bus DATA_0 bus DATA_1 or idle enabled HIGH HIGH Receive-only HIGH LOW disabled Go-to-sleep LOW HIGH error flag set[2] error flag reset wake flag set[2] wake flag reset wake flag set[2] wake flag reset float[3] Standby LOW LOW Sleep LOW X float float |
Similar Part No. - TJA1080A |
|
Similar Description - TJA1080A |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
