CS2300-OTP

DS844PP1

11

(518 ms to 634 ms) after CLK_IN is removed (see Figure 5). This is true as long as CLK_IN does not glitch

or have an effective change in period as the clock source is removed, otherwise the PLL will interpret this

pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl parameter; See

“PLL Clock Output” on page 16. If CLK_IN is re-applied after such time, the PLL will remain unlocked for

the specified time listed in the “AC Electrical Characteristics” on page 7 after which lock will be acquired

and the PLL output will resume.

eter will have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 6). Once

CLK_IN is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT

state will be determined by the ClkOutUnl parameter during this time.

PLL_OUT continues while the PLL re-acquires lock (see Figure 7). When ClkSkipEn is disabled and

CLK_IN is removed the PLL output will continue until CLK_IN is re-applied at which point the PLL will go

unlocked only for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl

parameter during this time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

= invalid clocks

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=0

Lock Time

CLK_IN

PLL_OUT

UNLOCK

ClkSkipEn=0 or 1

ClkOutUnl=1

Lock Time

= invalid clocks