9

7647DS–AVR–08/08

ATmega16/32/64/M1/C1

2.1

Block Diagram

Figure 2-1.

Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega16/32/64/M1/C1 provides the following features: 16K/32K/64K bytes of In-System

Programmable Flash with Read-While-Write capabilities, 512/1024/2048 bytes EEPROM,

1024/2048/4096 bytes SRAM, 27 general purpose I/O lines, 32 general purpose working regis-

ters, one Motor Power Stage Controller, two flexible Timer/Counters with compare modes and

PWM, one UART with HW LIN, an 11-channel 10-bit ADC with two differential input stages with

programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Individual

Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power sav-

ing modes.

Flash Program

Memory

Instruction

Register

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Interrupt

Unit

SPI

Unit

Watchdog

Timer

4 Analog

Comparators

DAC

ADC

PSC

Timer 1

Timer 0

HW LIN/UART

CAN

Current Source