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AT28BV256-20JI Datasheet(PDF) 10 Page - ATMEL Corporation |
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AT28BV256-20JI Datasheet(HTML) 10 Page - ATMEL Corporation |
10 / 18 page 10 0273J–PEEPR–10/06 AT28BV256 17. Programming Algorithm(1)(2)(3) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Data protect state will be re-activated at the end of program cycle. 3. 1 to 64 bytes of data are loaded. 18. Software Protected Program Cycle Waveforms(1)(2)(3) Notes: 1. A0 - A14 must conform to the addressing sequence for the first three bytes as shown above. 2. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 3. OE must be high only when WE and CE are both low. 16. Page Mode Characteristics Symbol Parameter Min Max Units t WC Write Cycle Time 10 ms tAS Address Set-up Time 0 ns tAH Address Hold Time 50 ns t DS Data Set-up Time 50 ns tDH Data Hold Time 0 ns t WP Write Pulse Width 200 ns t BLC Byte Load Cycle Time 150 µs tWPH Write Pulse Width High 100 ns LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(3) LOAD LAST BYTE TO LAST ADDRESS(3) ENTER DATA PROTECT STATE WRITES ENABLED(2) tAS tAH tWP tWPH tBLC tDH tWC tDS |
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